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An S-100 Bus FPGA Board.        
  FPGA Board

A field-programmable gate array (FPGA) is a natural extension of CPLD's and those a natural extension of the GALs we used on earlier boards.  It is in effect an integrated circuit designed to be configured by a customer or designer after manufacturing – thus the name "field-programmable". The FPGA configuration is done using a "hardware description language" (HDL).  There are two major languages Verilog and VHDL.

Verilog was created by Prabhu Goel, Phil Moorby, Chi-Lai Huang and Douglas Warmke around 1984. Originally, Verilog was only intended to describe and allow chip hardware simulation. The automated synthesis of subsets of the language to physically realizable gates etc. was developed after the language had achieved widespread usage. Verilog stands for the words "verification" and "logic". There were many upgrades/extensions over the years. The last major version appeared in 2005.

VHDL was originally developed for the U.S Department of Defense in order to document the behavior of the ASIC chips that supplier companies were including in equipment. Because of this background much of the syntax was based on the Ada programming language. The language has undergone numerous revisions and has a variety of sub-standards associated with it that augment or extend it in many ways, the last major release being in 2008.

Usage between the two tends to be polarized. Probably because of its Ada/Pascal style VHDL seems to be more popular in Europe.  The "C'" style syntax Verilog seems to be more popular in the US. 

Overlaid upon this are the chip "hardware camps".  Just like the original CPU chips, there are a number of FPGA chip manufacturers.  However there are two dominant players Altera and
Xilinx and Altera.   Recently Altera was acquired by Intel so i will refer to is as Altera/Intel.  Much of the information on the web still appears under the name Altera.   Both groups by now seem to have endless variations of their FPGA chip families.   The major ones are:-

Xilinx -- Spartan
Altera/Intel -- Cyclone.

Both companies provide extensive software to program their FPGAs.  The full blown "IDEs" are quite expensive to license but fortunately both companies now supply free "lite" versions. These lite versions are way more than adequate for our needs.

This brings me to the third component in our decision process,  picking an FPGA and programming it.   There are two fundamental ways (these days) you can program these chips. You can use the above two traditional programming languages (Verilog and VHDL) or,  you can program the FPGA using essentially a schematic and a graphic interface.  Both are available within the Xilinx or Altera/Intel IDE's .  The latter produces a special file called a
"Block Diagram File" (.bdf).  The IDE software understands this file (it actually internally makes a Verilog or VHDL file)  to program the FPGA.  The whole process is somewhat like writing a web site page.  You can either write the whole page yourself in HTML or use something like I'm using here (Expression Web),  to "draw" a web page in blocks, graphics etc.

Again, usage between the two approaches by people tends to be polarized.  The good news is that within IDE's you can import and export modules for both types.  You can for example see/export the Verilog code that makes up a complex BDF module or you can convert a Verilog module into a BDF module.

Coming from by now, years of experience using KiCAD to lay out  over 100's of S100 bus PC boards I personally found the BDF approach of programming an FPGA very easy. Within a day or two I was up and running programming an FPGA with quite complex circuits.   This was possible because the IDE supplies things like all the common 74xx logic chips, many of the common VSLI style chips (e.g.. UARTs),  and contains many libraries of many extremely complex/useful modules such as CPUs.  While you can drill down for detail,  at a top level they behave as "black boxes". You just supply the wire or bus connections -- which you draw as lines.   It would take me months of learning to do the equivalent in raw Verilog code.  I will illustrate this below.

However first we have to decide on the hardware and software!  After a brief analysis,  I decided on the following setup:  I will work with a Altera/Intel Cyclone IV FPGA and use the Altera/Intel Quartus Prime V18.0 Liet IDE (in Windows 10).  A major factor in the choice of the Cyclone IV is that it is available as a socketed adaptor board.  The company Waveshare supplies a number of these adaptor boards.   Many of the major/recent FPGAs come only in a BGA format.   Clearly soldering chips like this is outside the capabilities of most of us. We will use their "CoreEPCE10" Cyclone IV board adaptor. Its schematic can be seen here.
This brings me to another "catch" with FPGAs.  While the chips can be programmed and reprogrammed indefinitely, all the information is lost when the power is turned off.   Normally you burn your program into Flash RAM which the FPGA then reads on power-up.  Few FPGAs have the Flash RAM within the chip. Most require a connection to a serial line connected Flash RAM on the actual PC board.  Fortunately the CoreEPCE10 already has this arrangement on the adaptor onboard -- in the form of a EPCS16 serial (16MB) Flash RAM chip.  This is essentially an SPI Flash device, with the physical interface consisting of the signals: MISO, MOSI, CS and CLK connected to a JTAG programming socket -- just like our CPLD chips. The Cyclone IV uses the first 256 words as a kind of  ‘boot-rom’. The rest is your own FPGA program.

One other issue using most FPGAs is the voltage(s) they require.  The Cyclone IV requires 1.2V, 2.5V and 3.3V inputs.  Normally one would have to supply 3 voltage regulators on a PC board.  The CoreEPCE10 does this from a single 3.3V supply.

Finally we come to the last hurdle; With a 3.3V power supply we need a "voltage level shifters" to interface with the normal 5V 74LSxxx TTL circuits in our S100 bus.   We have seen this problem before with our Edison and Edison II boards where in that case we had to shift from 1.2V to 5 Volts.  Fortunately shifting from 3.3V to 5V is far easier. A specialized 74LVC245 chips is built for this purpose. We have however to blanket all pins on the FPGA with this chip. Any 5V input to the FPGA will irreversibly damage that chip pin and possibly the whole (expensive) FPGA.

The Board.
Broadly speaking our first FPGA board will be loosely modeled on our Edison II board.  With programming,  this FPGA board can (in theory), be configured to behave as almost any S100 bus board. Either as 1970's legacy boards or our own recent S100Computers boards. 

One thing that actually takes a bit of time to realize is how programmable these chips are. As we will see below, even with every major S100 bus pin "taken care of"  in our applications,  we have not used up even close to 1% of the FPGAs total gates capacity.   The CoreEPC10 unit has a total of 244 programmable GPIO pins.  The Cyclone IV actually has more, but they are used on the adaptor board for programming, diagnostic LEDs etc.  With that number of GPIO pins one feels like a kid in a candy store.  Unlike situations like for example the Edison CPU board,  where one has to multiplex pins,  in this case we almost always can work with dedicated I/O pins.    These pins BTW can be configured as inputs, outputs or bidirectional.   Our first "application" will be to program the board to behave as a simple port I/O board.  Later we will work up to more complete situations where the board will act as a true CPU driven bus slave or indeed a bus master.    Yes, amongst the modules for the Cyclone IV are very powerful CPU modules!  There require very complex FPGA coding, but again, it's all done for us as a "black box" which one can easily utilize.

Here is a very oversimplified diagram of the board layout.
  FPGA Board layout Diagram

The board has a some 46 5V I/O connections at the top of the board that may be used with an S100 bus daughter board for any application you might come up with. Over time I anticipate most of our applications running on these daughter boards.  They should all plug into these connector pins.   At any time one has absolute control and access to any S100 bus line. In a bus master configuration it could be in fact be the only CPU in the S100 bus.

Programming the Cyclone IV FPGA
Please keep in mind that programming an FPGA is different from the normal linear/sequential programming approach you may be used to.  On an FPGA everything is potentially happening at once.  Good FPGA programmers take years to excel and currently are in high demand.   Timing and power distributions across the chip almost become an art form.  Fortunately out needs will be far simpler.   Also there seems to be an excellent community of experienced people ready to help -- beginners.  I have found the Altera forum to be very useful and helpful.   However by far the best way to get started is to look at a few YouTube demonstrations.   

One outstanding YouTube video to get you going with Block Design File FPGA programming is this one by ClockFabrick Electronics Academy
A text summary is provided here. With just that video alone you can do some serious work. 
Another pair of excellent videos is from the University of Colorado,  Introduction to FPGA Design and Improving Productivity with IP Blocks.

Before we jump in to programming however, its nice to have a simple hardware test system to practice on. You can jump in and use the S100 board describe below directly but if you are a real beginner its nice to be able to flash a few LED's and read a few switches before you dig in deep.  At this level almost any FPGA will do.  There are many available.  I began with the Triasic DE0-Nano.
  DE0-nano   Wave Share Dev board Kit 
It's totally self contained,  all you need to do is hook it up to your PC USB port on a laptop.  I could not quickly find a simple video demo for programming a blinking LED for this board using Quartus with a BDF approach. However this one (PGA Tutorial: Blink an LED) using Virlog directly,  is very informative to get you going. 

I should point out that one useful thing about these boards is they are very helpful at the start to test out a simple module you may be developing.   You have 4 input switches and 8 output diagnostic LED's.  As a real beginner getting the hang of FPGA programming in Quartus (even while traveling) I could test code, modules etc. easily.   BTW, don't waste time with the Terasic software on their supplied DVD.  It does not seem to install/work correctly on Windows 10.  Typical of a Chinese company, great hardware, poor documentation/software. Just use the Quartus Prime IDE software directly.

WaveShare supplies a DVK600 kit (see the above picture), with a wide range of add-on's for FPGA program development with its Cyclone IV adaptor.  These will be very useful for developing and programming new FPGA driven S100 boards. Probably overkill for a beginner.

Quartus Prime.
The Quartus Prime IDE software package can be downloaded from this Intel site.  However you should first review this video about the installing process.  The whole Quartus Prime package is a large package, allow about 30 minutes to run the install.  If you use the Terasic development board it has its own FPGA programmer built in. Many others do also.  Most seem to utilize a "USB-Blaster" driver.    For the WaveShare unit you will need to get their USB-Blaster V2 to actually upload your code to the FPGA.
You can use the Terasic DE0-Nano to start programming an FPGA if you like.  It has 8 LEDs and 4 switches that allow you to do some sophisticated things.   However it's best you quickly get to using the WaveShare Cyclone IV FPGA.  That unit has 4 LEDs which can be programmed just by adding 3.3V power to the unit.   We will start with this.

Step By Step Building the FPGA Board
The build instructions are fairly simple for this board but because it is a complex board building it should not be rushed.  As always, first examine the bare board carefully for scratches or damaged traces, use a magnifying glass if need be.  A broken trace is almost impossible to detect by eye on a completed board.
Solder in all the required IC sockets, resistors, resistor arrays, capacitors, jumpers, and the Pololu 5V and 3.3V (LM3940) voltage regulators.  Do not add the LED's yet. Be sure you put the resistor arrays in with the correct orientation of pin 1. Check their values before soldering (they are difficult to remove).  Insert all jumper arrays.
For prototype boards I generally use "double swipe" IC sockets. For a critical board like this I prefer to use "Machine Tooled" IC sockets.  However they are more expensive and you have to be particularly careful not to bend the IC pins.  The 2MHz clock oscillator can have its own special sockets (e.g. Jameco #133006) but actually I find the "Machine Tooled" IC sockets make a better connection.  I in fact solder the 2MHz oscillator (P7) directly to the board since it will never be changed.
Place the board in the bus. There are two separate voltage rails on this board 5V and 3.3V. Carefully examine the schematic and check the voltage to the individual sockets are either 5V or 3.3V.  It is absolutely critical the FPGA adaptor pins never sees a 5V voltage.  

BTW, your system should boot and run correctly with its Z80 master CPU board. If not, you have a serious solder bridge somewhere on the board.  Before you do anything else with a magnifying glass go over every socket on the board and examine for proper solder joints. I like to "reheat" each joint just to be on the safe side. The silk screen/varnish on these boards us quite thick. It's easy not to have a good solder joint for the ground pins.  Double check.   Extra time here will save you hours later, (Been there, done that! ). 

Next insert all 6 LED's. Before soldering them in place ground the appropriate pin to be sure they are OK.    (I always use a blue LED for D7 "Slave Active"  in my systems). 

There is one major construction decision you need to make with this board right at the start.   The WaveShare unit uses unusual 2mm dual row pin connectors. Unlike to normal 0.1" connectors these are quite rare an expensive (Digi-Key #S5750-30-ND) .  If you solder these female sockets to the board the WaveShare adaptor sits quite high on the board and will prevent the next S100 bus slot from being used.  If you carefully remove the JTAG socket on the board and use a right angled 2x5 pin connector you will be OK.   Alternatively you can solder the adaptor directly to the S100 board. Of course removing the adaptor is all but impossible in this case.  While I don't recommend it, I have found that the pin fit is so tight that you can get away with just pressing the adaptor into the board during debugging development.

BTW,  the KiCAD footprint for this adaptor board took me three prototype boards to get it exactly right. If you ever want to do your own board I suggest you start from this board. The large number of pins allow no margin in the fitting. 

We will first program the WaveShare/Cyclone IV FPGA just to flash there 4 LEDs on the adaptor board. For this all we need is the two above voltage regulators and the WaveShare adaptor attached to the S100 board.  Here is a picture of this setup.

Programming The FPGA.
Launch Quartus Prime and load the program
Demo_01.bdf.   All the .bdf files we will use are supplied at the bottom of this page.  Typically you would make a folder:


It is very useful to have before you a printout of the FPGA board schematic and the WaveShare schematic.  The latter for example shows the FPGA pins for the on-board LEDs. In all our programs its critical the correct FPGA pins are associated .bdf file pins.  Also make sure that Quartus Prime knows/assumes you are, (in this case), utilizing the Cyclone IV EP4CE10F17 chip.  Before going forward, now is a good time to take another look at the ClockFabrick Electronics Academy video.

Here is the very simple Demo_01.bdf program.  It simply flashes the 4 LEDs on the WaveShare adaptor board.
If you have watched the above video the above
.bdf program is obvious and trivial.
Here is a picture of the relevant Programming Dialog Box.
    Programmer Dialog Box
The actual compiling and programming process does take longer than you might expect (~30 seconds for the above).
You must get the above Demo_01.bdf program to work before going further. Here is a picture of the programming setup.


Please come back later

Cyclone IV numbers...


A Production S-100 Board
Realizing that a number of people might want to utilize a board like this together with a group of people on the  Google Groups S100Computers Forum, "group purchases" are made from time to time.  Contact and join the group if you would like to be involved in this project.  Please see here for more information.

The links below will contain the most recent schematic of this board.
Note, it may change over time and some IC part or pin numbers may not correlate exactly with the text in the article above.

Most current KiCAD files for this board    (V0.5C Prototype zip  files  7/16/2018)

Other pages describing my S-100 hardware and software.
Please click here to continue...

This page was last modified on 07/18/2018