This board met all the electrical and timing specifications for the IEEE-696
S-100 bus standard. It had a capacity of 64K bytes, but was available in
16K, 32K, and 48K versions to OEMs. The 16K and 48K versions were eight-bit
only. The memory itself was organization as 64K by eight bits. Sixteen
bit transfers access two bytes simultaneously as specified by the IEEE-696
standard.
The board had extended 24-bit addressing but could be set to ignore upper
eight address lines in systems with only a 64K address space. The board
could start on any 64K boundaries in the S-100 16MB address space. 32K
versions could be addressed on any 32K boundary. High speed 100 nsec
chips were normally used. Memory access time from pDBIN high (assuming
address setup time has been met) was about 59 nsec.
A minimum of only 45 nsec. was required for the MWRITE pulse width.
The board did however suck down 2.5 amps when fully loaded.
The manual for this board can be obtained
here.
