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A 1MG RAM & E-PROM S-100 Memory Board
  Production Board Picture
 
Introduction

Our original EPROM S-100  board proved very popular. All production quality boards were quickly taken.  A second "V2" version of the board was later made. That too went quickly.  A number of people have requested an "All in One" RAM/ROM combination board capable of working in 8 or 16 bit S-100 systems with pre or post IEEE-696 CPU boards and capable of accepting a wide range of UV-EPROMS, EE-PROMS, Static RAM chips and Flash-RAM chips.  Also in view of the range of chips and CPU's a flexible wait state circuit that can independently assign 0-8 wait states to the above chips would be desirable.  Finally, it would be nice if the EPROMs could be phantom/shadowed in or out  depending on which CPU is controlling the S-100 bus.  For example one normally would not want a Z80 monitor at F000H if the bus has given control to an 8086 in a 1MG address space.

In an attempt to address these needs I present the above board.  It should meet the above requirements, the only catch is that in order to do this one has to very carefully configure the board for the diverse range of memory chips it can accommodate.   This requires a careful analysis of each memory chips I/O pins, matching the boards jumpers accordingly.  Also one has to match switches and jumpers with the desired range of address you wish the RAM chips to reside in for the S-100 buss's address space.  This can be a little challenging.  To get people started I will provide a small sample of possible combinations. 

A common example will be illustrated that is configured to contain:-
    An 8 bit 28C64 EE-PROM at C000H (for say a Z80 Floppy Disk Controller BIOS).
    One Meg of Static RAM from 0H to FFFFFH (for the 8 bit Z80, and a 16 bit 8086 CPU).
    A 16 bit pair of 28C256 EE-PROMS at F0000-FFFFFH containing a monitor for the 8086.

    Zero to 8 wait states can be added to the EPROMS if needed (and if needed, the RAM).
    The 8 bit EE-PROM will not be active if the 8086 is controlling the bus. It reappears if control is passed back to the Z80.


However before we jump into describing this board lets review the pinouts of the more common EPROMS and RAM chips again:-
The board will accommodate the following types of storage chips:-

In 8 bit mode and for RAM addresses < 64K

EPROMS        2716, 2732, 2764
EEPROMS      28C16A, 28C17, 28C64A

In 16 bit mode and for RAM addresses 0 - 16MG

UV-EPROMS    2716, 2732, 2764, 27128, 27256, 27512, 27C010 (128X8), 27C020 (256X8), 27C040 (512X8), 27C080 (1MX8)
EEPROMS        28C64, 28C256, 28C512
FLASH RAM     CAT27F010 (128KX8)
STATIC RAM    HM628128 (128KX8), AS6C4008 (512X8)

There are a many other chips (and equivalent brand name chips) that can also be used by adjusting the jumpers.
I just have not tested them out yet.


PROM/RAM Pin Jumpers.
The board will accept numerous 5 Volt EPROM, EEPROM, FLASH and RAM chips.  That's the good news. The only catch is you have to be careful with what jumpers you use for each chip type. Here are the configurations for the most common memory chip types:-

For 8 bit EPROMS that reside in socket U123:-
 
    
EPROMS 8 Bits
          
For 16 bit EPROMS that reside in sockets U4 and U121:-
  

      EPROM1 Jumpers
  EPROM2 Jumpers
  EPROM4 Jumpers
     
Note: All EEPROMS (electrical erasable, rather than UV light) of the equivalent capacity above will have the much the same pinouts/jumpers. However in a few cases where there are differences. For example with 27C256 EPROM's and 28C256 EEPROM's. So always check the pinouts. I made this mistake with 28C256 EEPROMS only to have them re-programmed in a 27C256 socket setup!

For 16 bit EE-PROMS that reside in sockets U4 and U121:-
    
EPROM3 Jumpers
  

For a pair of 128K X8 FLASH RAM's (16 Bit) in sockets U100 and U101:-
  

128K Flash
       
Note you do not have to use the full 128K of Flash RAM. By adjusting (see below) the RAM/ROM window that activates 16CS* using SW2 and IC2A you can select sections of the chip and surround the rest with other S-100 RAM on the bus.  The other RAM board however must recognize the S-100 Phantom line (pin 76). The 4MG Static RAM board  is an example of this.

For a pair or Static RAM's (16 bit) in sockets U100 and U101:-
    

Statis RAM
 
S-100 Bus 8 & 16 Bit Data Paths
This is a repeat of the discussion on the 4MG RAM Board -- The S-100 bus was designed around the 8080 CPU. This CPU has a bi-directional 8 bit data path, however because Ed Roberts wanted to control it via a series of front panel switches, the CPU data bus was broken out into separate 8 bit Data In and Data Out paths on the S-100 bus.   This worked fine. RAM boards had their RAM chips connected to both data paths and I/O boards were likewise connected.   It was a somewhat inefficient setup but it worked (all for a simpler front panel).   The first diagram below shows the basic layout.
  
   8 and 16 bit systems
  
  
When 16 bit CPU's came along things got more complicated.  All 16 bit CPU's have a 16 bit bi-directional data path.  They can interface directly to RAM chips that are 16 bits wide or two 8 bit wide RAM chips. In the early 80's the latter type of RAM's were much more common. Two 8 bit wide RAM chips differing only in address line A0 (0 or 1), would be connected to the 16 bit bus.  The S-100 Data In and Data out lines were utilized together as a single bi-directional 16 bit bus and were connected via buffers to the CPUs 16 data line pins.

Now if all you were going to use was such a 16 bit CPU that would be fine. But such a setup would not work with older 8 bit RAM cards or indeed with any I/O cards which also expect a split 8 bit interface.

The solution was simple and elegant and the heart of the IEEE-696 standard. For 16 bit systems the bus behaves as a 16 bit bidirectional bus. For 8 bit systems a bridge buffer on each RAM board transfers the data coming and going to the board over separate 8 bit data lines depending on whether it's address is odd or even. If we have 8 bit data coming to the board on an even address, it travels on the "Data Out" path and goes directly to the A=0 RAM bank.  If instead the 8 bit data is destined for an odd address it arrives as before at the RAM board top buffer but then is dropped down to the lower A0=1 RAM bank  via a bridging buffer.

If the 8 bit CPU wants to read a even address it activates this buffer in the opposite direction so the RAM A=0 bank data is shifted down to the S-100 data in lines. If the 8 bit CPU wishes to read am odd RAM address the A0=1 RAM bank data travels directly to the  CPU on the Data Out bus.

The hardware logic to do this is quite tricky. You need to factor in if we have a CPU read or write, if the data is 8 bits or 16 bits wide and if the destination address is on an even or odd address line.  (Fortunately no common 16 bit CPU transfers 16 bit data on an odd address line).

Now back in the mid 80's companies like CompuPro and Macrotech implemented this logic in ROM like chips called
PAL's. Unfortunately they never published the code.  


The Circuit
I wanted to build a S-100 PROM board that would serve me well into the future. Where I could use it with very fast and wide CPU's. I wanted to stick with DIP type chips. There are higher density PROM chips than the 512K/chips we use here but many require SMT. These are difficult to work with.   I have had good success with the 32 Pin DIP Alliance AS6C4008 (512KX8 Static RAM) chips, (Jameco Part #1927617) with the 4MG Static RAM Board. I wanted to be able to use this chip again here.

The board utilizes 74LS682's for RAM addressing. If you are unfamiliar with this technique click here.

The hardest part was figuring out a
PAL equivalent circuit using standard TTL chips. I came up with the following "7400" TTL layout.  It takes a few chips as opposed to a single PAL chip, but it is fast and reliable.
    
PAL Circuit

 
This PROM board is really three boards in one. It's an 8 bit EPROM board for an EPROM that resides in < 64K of the S-100 bus address space and two 8 or 16 bit EPROM/RAM boards for any address from 0 to 16MG.   The former is for use with 8080/Z80 CPU's. Very useful is the fact that both sections can reside together and overlap on the board. A typical application might be CPM3 and/or CPM with a memory disk. Note however, these applications require a CPU board that can address above 64K (Intersystem's, Compupro etc).  The board can accommodate up to 1MG of 8 bit RAM.  Remember also, that to program EPROMs for 16 bit CPU's you have to program the "Low Byte" in one EPROM and the "High Byte" separately in the other EPROM pair.
  
The board has three independent buffers to place data on the S-100 bus. These are controlled separately by three signals 16CSA*, 16CSB* and 8CS*. The circuit is arranged so both the board data output buffers/EPROMS cannot come on together.  Note the many RAM/ROM jumpers are now combined more efficiently into two sets or 3 jumper rows as shown here:-

   
  Board Jumpers for ROMs

  
Here is a schematic of the board jumpers for most common static RAM chips.
    
  Board Jumper for RAMs
  
You will note that we have also added a battery backup  circuit so that the static RAM chips can retain their contents when power is turned off.
There are two battery sources. An on-board coin 3V battery and a connection if needed for an external battery.  Many of the newer static RAMs can retain their contents for months with such a 3V battery.  This function is taken care of completely by the 8 pin Maxim DS1210 Nonvolatile Controller chip.


The actual range of addresses that the RAM or ROM chips are active is also determined by jumpers and switches on the board.   The arrangement is very flexible with the 3 board components (8 Bit ROM, 8/16 Bit ROM and 8/16 Bit RAM) each settable separately.
Here is a schematic example for the RAM circuit:-
 
   
     RAM Address Jumpers
  
  
The switches and jumpers utilizes 74LS682's for addressing. If your are unfamiliar with this technique click here.

  
Finally you will notice for the CAT28F010 FLASH RAM's (Jameco Part #242608), the CE* is tied to ground (rather than 16CSB*).  The reason for this is that these Flash RAM's go into a "Low Power Mode" when CE* is high. There is a latency time required for the chip to "warm up" after CE is brought low. Keeping it low avoids the problem. The chips are low power anyway!  This unfortunately does mean that FLASH RAM chips cannot be used at the same time as EPROM's in the U4 & U121 sockets. 

A typical layout of a board in a Z80/8086 dual CPU system might look like this:- 
   Memory Map
    
The boot Z80 monitor EPROM/EEPROM would reside at F000H in RAM.  With a Z80 CPU board like the Intersystem's board or our own Z80 CPU board, the rest of memory could be used for CPM3 banks and/or as a memory disk.  This is what I do in my system. If a 8086 CPU has control of the bus  then it will first start from the reset address FFFF0H in RAM. Here it would find the end of the 8086 Monitor (in a pair of 28C256 EE-PROMS). From there it would jump to the start of that monitor (at F8000H). Amongst the commands would be one to boot CPM86 or MS-DOS. 

There are two things to keep in mind with the above arrangement. First, the static RAM 512X8 pair occupy the entire 1MG address space. The circuitry on the board insures that these RAM chips are not activated if any of the above 3 EPROMS are addressed.   See below. Note, by adjusting the switches SW1 & 2 one does not have to utilize the entire 1MG of RAM, (if for example you would like to test another S-100 bus RAM board).  

For the 8 bit EPROM at F000H-FFFFH, if it is addressed, the line 8CS* will go low. This inactivates any output from the
PAL like circuit. Instead it activates its own S-100 bus buffer (U125).

For the 16 bit EPROMs at F0000H-FFFFFH, they are addressed by 16CSA* going low. This same line can be used to inhibit 16CSB* (Board RAM), which normally activates the static RAM chip pair (U100,U101) by jumpering P2-5 to P6-5 and setting switch SW2, position 5 high.  This way the EPROMs create a "hole" in the boards 1MG Address space.

One final thing, we normally don't want the Z80 EPROM to be active when the 8086 CPU is controlling the bus.  The 8086 gets control of the bus when the S-100 signal TMA0* signal goes low.  Again look at the schematic, by jumpering P29, 1-2 and connecting P17 1-2, if P19,7 is connected to P21,7 setting SW4 pin 7 high will inactivate the circuit (8CS*) in TMA0* goes low. This way we can insure that this EPROM is never active when the 8086 has control of the bus.   Please note however for this to work on any of our slave CPU boards the appropriate TMA0-3 line must be pulled low on the S-100 bus.  If you use the CPUs onboard port to activate the slave, you must also add the appropriate jumper to lower the S-100 TMA line.  For example on our 8086 slave CPU board jumper P36 1-2 and 3-4.

 
The Final EPROM S-100 Board
The above board had worked without any problems in two systems using CPM+, CPM86 and MS-DOS with a verity of hardware configurations so I decided to go ahead and do a final commercial type board.  The trace layout was optimized further before doing this.  We moved all the RAM and ROM jumpers to two sets of jumpers.

(BTW, I would like to extend a big thanks to Tom Lafleur who help greatly in fine tuning and optimizing the final version of this board.  Thanks Tom, a much better board).


Step By Step Building The Board.
You will need a printout to the board's schematic and chip/jumpers diagrams, both available at the bottom of this page.

The first step is to examine the board carefully for scratches or damaged traces. Use a magnifying glass if need be. The quality of the boards we get is excellent. I must have done 37 by now, never had a problem, but there is always a first time. A broken trace is almost impossible to detect by eye on a completed board.

Next solder in all the required IC sockets, resistor arrays, capacitors, jumpers, the switches SW1 to  SW5 and the 5 Volt  regulator.  Note there is a +5 volt trace coming from the 5 Volt regulator on the front of the board. To be sure the heat sink does not touch it. It's best to use a mica TO-220 insulator (or put a nut washer between the heat sink and board).  I like to use 3A TO-220 regulators (e.g. LM323T's - Mouser P/N 511-LM323T) but a 1.5A regulator is probably fine also.

Do not yet add the 9 LEDs yet.  Be sure you put the resistor arrays in with the correct orientation of pin 1.  Check their values before  soldering (they are difficult to remove). 

For prototype boards I generally use "double swipe" IC sockets. For a critical board like this I prefer to use "Machine Tooled" IC sockets.  However they are more expensive and you have to be particularly careful not to bend the IC pins. 

Check the voltage to sockets on the board is about 5V by placing the board in your S-100 system using an extender board. With no load you will typically get between 4.9 and 5.1 Volts.  BTW, your system should boot and run correctly with its Z80 CPU. If not, you have a serious solder bridge somewhere on the board.  Before you do anything else with a magnifying glass go over every socket on the board and examine for a proper solder joint. I like to "reheat" each joint just to be on the safe side. The silk screen/varnish on these boards us quite thick. It's easy not to have a good solder joint for the ground pins.  Double check.   Extra time here will save you hours later!

We will now build the board up in functional steps. Avoid the temptation of adding everything at once and popping it into your S-100 box. Step by step is faster in the end -- trust me.

First add the LEDs D1-D9.  The color choice is up to you. I use always use a Blue LED for board select in my system.  To check you have each LED orientated correctly insert in the board hole temporally grounding (one at a time) pins 3,5,7,9,12,16 of U3 and bringing pin 18 to 5Volts. The LED should light up. Only then solder in place.  Here is a picture of the board at this stage:

The 8 Bit ROM Section
This board consists of 3 sections. An 8 bit ROM section, a 8 or 16 bit ROM section and an 8 or 16 bit RAM section.  We will build and test the board one section at a time. First the 8 bit ROM section.  For testing we will use an 8K 28C64 EEPROM. We will for testing purposes place it at C000H in a Z80 64K memory address space. This EEPROM will contain our Z80 Monitor (Master.Z80) assembled with an org. at C000H.  So if the ROM is functioning correctly a jump to this location should have it signon.

Add U20,U21,U3.
Add U8,U11,U14, U5, IC3, IC4, U1 and U124.
Next add U2 but for now bend out its pin 4.
Jumper P31 5-6.
Jumper P19 1-4 to P21 1-4,   P20 5&6 to P21 5&6,  P19 7&8 to P21 7&8.
Jumper K7 1 to 2 and P17 1 to 2.
Add JP1 if your S100 bus does NOT have another board pulling the Phantom* line high

For an 28C64 EEPROM jumper K31 2 to 3, leave K22 open.
Jumper P32 1 to 2 and add U125 and U10.
Add U2 and U17.
Here is a picture of the board at this stage.
  
  8 Bit Support Chips
 
If you do a Z80 monitor memory map ("A "command) you should see a map like this:-
  
  8 Bit memory map
  
Note there is no code at C000H at this stage because we have not added the EEPROM.  Next add the EEPROM (U123).  The EEPROM monitor code should be visible and you should be able to jump to C000H and have the monitor signon.

The 16 bit ROM section
Next we will add the 16 bit ROM section.  We will utilize our Z80 CPU board as well as a slave 8088, 8086 or 80286 slave board to test our 16 bit circuitry.  Initially we will place a 8086 monitor at C0000H in RAM for testing.

bend in pin 4 of U2.
Add IC5, IC4 U19, and U5.
Jumper P18 1- 8 to P25 1-8
jumper P16 1-6 to P24 1-6,  P27 7&8 to P24 7&8
Jumper P26 1-2 and P28 1-2.
Jumper P32 1-2 and P30 3-4.
Set SW6 and SW5  with all switches closed (ground).
Add U15,U16, U18, U13, and U25.
Check the board does not hang the bus.
If Ok add U22, U23 and U24.
Add JP6

We now need to correctly configure the address lines and chip select lines for the two EEPROMS.  This has to be carefully done. Consult the diagrams at the top of this web page to be sure you are hooking the chips up correctly.  Double check, it is easy to get things wrong. This is the price you pay for a very flexible RAM/ROM board!.
Configure the following jumpers:-
P8,6 to P13,6 (pin1 to A15)
P8,4 to P12,4 (pin 28 to Vcc)
P8,14 to P12,14 (pin 27 to Vcc)
P8,7 to P13,7 (pin 26 to A14)
P8,8 to P13,8 (pin 23 to A12)
P8,10 to p13,10 (pin 23 to A12)
P8,18 to P13,18 (CE* to 16CSA*)
P8,17 to P13,17 (OE* to E*)
P8,16 to P13,16 (OE* to D*)

Here is a picture of the board at this stage.
 
  16 Bit ROM Addition
     
 
If you switch over to your 8086 Monitor and do a memory map display you should see a picture like this:-
  
  16 Bit memory map
      
If you use your 8086 monitor and jump to C000:0000H your 8086 monitor at C0000H should sign on.
A few points to remember; 16 Bit ROMS will have their address lines as AD+1 because they are accessed by the CPU as words. Take care when you assemble the 8086 monitor that you configure it to start at an offset of 0H for the above test (set 80286 = TRUE).  If you set 8086 = TRUE then jump to C000:8000H.  One nice thing about 8086 code is it will run in any segment unchanged.

The 16 bit RAM section
Next we will add the 16 bit RAM section.  We will utilize our Z80 CPU board as well as a slave 8088, 8086 or 80286 slave board to test our 16 bit circuitry.  We will place the RAM in the first MG of the S-100's 16M address space (0H-FFFFFH).  So we will remove any current RAM board in the system.

Add IC1, IC2 and U6 the DS1210 chip.  Add a coin 3V battery (CR2032) with the + side facing up.
Jumper P1 1-4 to P5 1-4, P3 5-8 to P5 5-8

Jumper P4  1-4 to P6  1-4
Set SW2  1,2,3&4 to closed (ground)
Set SW1  1-8 closed (ground)

We will utilize two 512K AS6C4008 Static RAMS. We need to correctly configure the address lines and chip select lines for two RAM chips.  This has to be carefully done. Consult the diagrams at the top of this web page to be sure you are hooking the chips up correctly. 
Configure the following jumpers:-

P14 3 to P16 3  (Pin1 to A19)
P14 6 to P16 6 (pin3 to A15)
P14 12 to P16 12 (pin 31 to A16)
P14 4 to P16 4 (pin 30 to A18)
P14 8 to P16 8 (Odd pin 25 to A12)
P14 10 to P16 10 (Even pin 25 to A12)
P14 15 to P16 15 (Even WE* to G*)
P14 14 to P16 14 (Odd WE* to F*)
P14 17 to P16 17 (Even OE* to E*)
P14 16 to P16 16 (Odd OE* to D*)  

Jumper P31 3-4 (16CSB*)

Because we are now using the board to provide the systems total RAM. We need to make sure the above RAM chips are not activated if the onboard ROM (8 or 16 bit) or an external CPU board ROM try's to access this memory circuit.   For the onboard 8 bit ROM,  8CS* activates U125 but inactivates the 16 bit circuit (*CS* to U15 and U16),  so we are OK. BTW, if you are using another RAM board you need to jumper K7 1-2  so Phantom* is activated for that board.  If you are using an 8 bit ROM on say your Z80 board you need to have IC2 recognize the Phantom* input line.  So P2 6 to P6 6 and SW2,6 to open (high).  I this way when an external ROM needs the address space it inactivate this boards RAM.

For 16 bit external ROMs (e.g. our 8086 or 80286 boards) we utilize the same Phantom* line.   If however we utilize the two onboard ROMs we utilize the 16CSA* input to IC2.  So P2 5 to P6 5 and SW2,5 to open (high).  This way when the two onboard ROMS are accessed 16CSA* goes low inactivating IC2 and 16CSB*.

There is one final complication. We usually will not want a Z80 Monitor (at C000H or F000H) to be active when control is passed to a slave CPU like our 8086 board. To inactivate the 8 bit ROM circuit we also factor in the TMA lines 0-3. If any of these go low TMAx goes low. This feeds via P19 7 to P21 7 and on to IC3. SW3,7 is left open (high). So 8CS* is never activated unless the master/Z80 is controlling the bus.

Insert the board in your system. If the RAM is working correctly your Z80 monitor should come up.  If not carefully step through the RAM selection path. Is 16CSB* low. If not check your jumpers and SW1 and SW2.  Check the P14 jumpers one more time. You should see the 8 Bit ROM at C000-CFFFH. Switching control over the 8086. You should see only RAM in low memory and (as currently configured) our EEPROM at C0000 - CFFFFH.

Inactivating the 8 bit ROM section
The most common setup with this board will probably be a Z80 board with its own onboard monitor (at F000-FFFFH), 1 MG of RAM and an 8086/80286 monitor in two 28C256 EEPROMs at F0000-FFFFFH.  In this situation we really would like the 8 bit ROM circuit to act like it is not there. Unfortunately removing jumper P31 5-6 (8CS*) will not inactivate U125. The input to U1 pin 12 also accepts 8CS* and would activate U125.  (Pin 12 of U1 should have been connected to P31 pin6).   Fortunately there is an easy workaround. We jumper IC3 so it never is activated. Jumper P20 8 to P21 8 and set SW4,8 high.  Now the board acts as a 1MG RAM board with 64K of EEPROM.   We will place an 8086/80286 Monitor in this ROM and place it at F0000-FFFFFH.  No extra wait states need to be added to the board (SW5).

Here is a detailed picture of the board with this configuration:-
   
  RAM&ROM Switches
   
  RAM & ROM Chip Jumpers
 
   
Please note that I have tried to get all the jumpers listed correctly in this writeup. However it is entirely possible I have made a few errors.
If you notice anything incorrect please let me know so others will not make the same mistake.

RAM memory Battery Backup.
I have not extensively tested the RAM backup battery capability of this board. With the DS1210 chip,  the RAM 16CSB* comes to its pin 5.  It is sent out on its pin 6 to the static RAM chips.  The 5V power supply to both RAM chips is also supplies on the DS1210 pin 1. This gets to the RAM with K3 jumpered 2-3. This way on power down, the DS1210 reduces RAM standby voltage to 3 volts - supplied by the battery.

If the computer is turned on but with the RAM battery backup function active, 16CSB* is supplied to both RAM chips via K2 jumpered 1-3 (use a wire-wrap jumper) instead of the usual K2 2-3 jumper arrangement.  Remember to also have K3 jumpered 2-3 in this mode. (You can actually remove the P14,19 to P16,19 jumper if you are in battery backup mode if you like).

To test the battery backup, fill RAM 0 to 1000H with say 33H. Display RAM and confirm these values. Switch off the power for 5 minutes. Then turn on the computer and re-examine RAM. The same values should be present.

Battery backup enabled
Jumper K2 1-3   
Jumper K3 2-3  

Battery backup disabled
Jumper K2 2-3
Jumper K3 1-2
Jumper P14 19 to P16 19  

David Fry has kindly provided a diagram of the board jumpers (see below).

Bugs.

I have not found any major bugs with this board so far. As already mentioned above the next version of the board will have pin 12 of U1D connected to pin 6 of P31.
The RAM section seems to work with all the CPU's we have done (Z80, 6502, 68K, 8088, 8086 and 80286, as well as our prototype 80386 boards), as does the ROM section. The recent 80286 board does not work well with the ROM section of this board unless it (the 80286 board),  is slightly modified -- as is mentioned for that board (RAM is OK however). On the next revision of the board K2 pins 2 & 3  will be swapped to allow a simple jumper to be used.   Also pin 28 of U101 should be connected directly to pin 28 of U100.
 

A 1MG RAM & E-PROM S-100 Memory Board  (V2).
The minor error mentioned above was corrected in the V2 version of the board and now has pin 12 of U1D connected to pin 6 of P31.
  
  V2 Schematic Corerction

This simplifies the isolation of the three separate components of this board (8 Bit ROM, 16/8 Bit ROMs, 16/8 Bit RAMs).  Some other minor changes/jumpers were added as well.  Here is a picture of the V2 board:-
   
  RAM+RAM V2 Board

Setting up the board still remains tricky since numerous jumpers are required to accommodate the many RAM/ROM chips the board can accommodate.   Perhaps the most common configuration is 1MG of RAM with an 8086 ROM monitor (28C256's) at F0000-FFFFFH.  Here are two close up pictures of the boards main jumpers for this configuration:-
  
  RAM+ROM Chip Jumpers (V2a)
   
  RAM+ROM Switches (V2a)

In this configuration the 8 bit ROM circuit is not utilized, so no jumper P31 5-6.


Source of Chips
Most of the chips on this board are quite common.  A good source of 74LSxx and 74Fxx chips is Jameco, Mouser or DigiKey.
The 512K Static RAMs can be obtained from Jameco,  #1927617.  27C256's the same, #39714.
The DS1210 can be obtained from Mouser, #700-DS1210.  I use their 3A V regulator's #511-LM323T.
The hole spacing for the coin battery holder are 23 mm apart on the board.  Many such holders are only 20 mm apart (e.g.. Jameco #355434). Fortunately the pins are long so you can bend the pins 90 degrees and then 90 degrees again to stretch then to 23 mm. Be careful however the pins are delicate.

MOST CURRENT EPROM BOARD  SCHEMATIC   (V1.0, 9/7/2013)
MOST CURRENT EPROM BOARD LAYOUT   (V1.0, 9/1/2013)
BOARD JUMPERS DIAGRAM PICTURE (V1.0 4/18/2014)
Most current KiCAD files for this board  (S100 EPROM V2-001 (1).zip   11/6/2014)

A second batch of these boards was done with the following small changes:-

1.    Connect pin 12 of U1D to pin 6 of P312.
2.   
Have ground pin option for pin 20 (CE) of U123.      
3.    Change the order of pins on K2 to avoid the need for wire-wrap

4.    Remove bA14 label on U100 and U101 and join U100 pin 28 to U101 pin 28 (both go to P14,7).



A Production S-100 Board
Realizing that a number of people might want to utilize a board like this together with a group of people on the  Google Groups S100Computers Forum, "group purchases" are made from time to time.  Contact and join the group if you would like to be involved in this project.  See if bare boards are available and/or see if you and others may be interested in doing another board run.
 

MOST CURRENT (V2b) EPROM BOARD SCHEMATIC    (V2b     12/3/2014)
MOST CURRENT (V2b) EPROM BOARD LAYOUT    (V2b     12/7/2014)
KiCAD files for V2.0b board
 (V2b    12/16/2016)
RAM+ROM V2.0b board BOM   (V2.0b    3/29/2017)

Other pages describing my S-100 hardware and software.
Please click here to continue...

 

This page was last modified on 03/29/2017