S-100 Bus Address & Data Line Selection with the 74LS682 Chip

Almost all S-100 board have some kind of Address/Port selection circuitry onboard.  For early boards this was often hardwired into the boards circuitry. As more and more boards became available manufactures started to add "jumper" circuitry to allow the user to add additional boards to their own system without hardware conflicts.

A typical circuit might be like this:-

With the above circuit, a port input or output buffer chip would be activated ONLY if the CPU addresses port 8FH (10001111B). If instead we used a circuit like this:-

Now if the CPU addresses ports 8FH or 8EH (10001110B or 10001111B) either one will be activated. The address line A0 no longer comes into the equation. In this way by playing around with the 8 inputs to the 74LS30 chip you can define what block of ports  you want to use.  For example suppose we wanted ports 2CH to 2FH (001011xxB) we would design the circuit as:-

There are many variations on this theme. Quite a number of 7400 type chips can and were used. For memory range addressing two sets of 8 input lines were decoded. However this function consumed quite a bit of board space. Once the ability to make 20 pin (and greater) DIP style IC's  become common and economical more sophisticated chips could be used. Again there were a few options, but in the end the 74LS682 chip seems to fill many needs.

In summary the chip output pin 19 will only go low if each of the P0-7 inputs exactly match the corresponding Q0-7 inputs. A nice feature of this chip (not seen for other similar chips) is the fact that if any of the Q0-7 inputs are unconnected, they will be pulled HIGH by internal logic on the chip.  So in our continuing example from above, ports 2Ch to 2FH would be selected with the following arrangement:-

One 8 position dip switch set and one 20 pin DIP IC takes care of the whole circuit.  By tying any of the P inputs low and matching them with the corresponding Q inputs (pulled low), you effectively take them out of the address equation logic. The remaining P inputs are then compared against the remaining Q inputs (High - switch open, Low - switch closed) to determine when to bring pin 19 low.

By connecting two or three 74LS682's together you can decode 16 bit data ports and the S-100 bus 24 address lines.   Let us take a practical example  -- suppose you wanted to activate a 2732 EPROM for a Z80 system that is IEEE-696 compatible (i.e. uses all 24 address lines).  Lets say you want to use it as a monitor at addresses F000H to FFFFH.  First look at the chip pinout:-

You will see that the chip itself utilizes address lines A0 to A11. So our chip (memory window) selection circuitry will need to extend form A12 to A23.

Put another way, any time the Z80 addresses memory between

0000 1111 0000 0000 0000B to 0000 1111 1111 1111 1111B memory CS* will go low.

Do try and get very comfortable with this chip address selection technique. I use it in almost all the boards I design.  In debugging a board, the first thing you should look at is:- Is pin 19 of the 74LS682 going low when a port or RAM is read or written to at the correct address.

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