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The PDP- J11 S100 Bus CPU V2 Board.
  Final Board
This is the second version of our original PDP-11 CPU Board.  It is essential that you become familiar with everything on that page before building and using this improved version of that board. The major modifications added to this "V2" board are:-

1.    The three 22V10 GALs on the V1 were condensed into a second 1508 CPLD.  There are no GALs on this board
2.    Code within this second CPLD allows for the handling of interrupts similar to how Digital did it for their PDP minicomputers. 
3.    The onboard UART now issues interrupts and behaves exactly as a Digital DL-11 Serial board when used with the PDP-11 Support board.
4.    A 10 pin ribbon cable connector is provided to directly interface with the PDP11 Support Board for timer and serial port interrupts.  
5.    The board resets the CPU correctly with a bus hardware reset.
6.    The board can output to a port to completely remove the onboard monitor ROM – and thus not interfere with Digital OS software.
7.    The board can output to another port to set the upper/lower half of the 28C64 and so effectively get almost 2x the code in it without using more RAM space.
8.    The board can output to another port to force the CPU into ODT mode.
9.    There is also a push button switch to force the CPU into ODT mode.

Apart from the addition of a second CPLD the main addition to this board over the V1 board is that this board now has is the ability to deposit an interrupt vector address directly on the PDP11 CPU DAL0-DAL15 pins.  The two 72LS374 buffers  that do this (U39 & U40) reside under the two ROM's.  Space is tight on this board so they must be soldered directly to the board within the ROM sockets themselves. Here is a picture of the relevant circuit.
 nt Vectors Circuit
How interrupts are handled on PDP11 minicomputers is a complex process, rather than repeat things on this page, please go to here on our PDP11 Support Board page for a full explanation.

To recap from that page -- the CPU on this board will issue the unique INTA vector request shown below.  This will activate the two buffers and place the de-multiplexed S0,S1 & S2 interrupt vector RAM address on the  CPU DAL0-15 lines. During this brief time all data in from the S100 bus is blocked.


!VEC_OE = LAIO3 & LAIO2 & !LAIO1 & LAIO0 & !BUFCTL;           /* Instruction INTA vector (1101) read request */

         'b'000 => 'h'38; 'b'001 => 'h'38; 'b'010 => 'h'38;   /* S2,S1,S0 => Active LOW */
         'b'011 => 'h'38; 'b'100 => 'h'38; 'b'101 => 'h'38;
         'b'110 => 'h'30; 'b'111 => 'h'38;

It is absolutely critical that this process is fast and 100% reliable.  Directly interfacing the above buffers to the CPU lines really helps this process.  The S100 bus is actually not involved.

Step By Step Building the PDP-J11 V2 CPU  Board
The build instructions are fairly simple for this board. It is essentially the same as for the original PDP11 board. However because it is a complex board building it should not be rushed.  As always, first examine the bare board carefully for scratches or damaged traces, use a magnifying glass if need be.  A broken trace is almost impossible to detect by eye on a completed board.

Build the board up in functional steps. Avoid the temptation of adding everything at once and popping it into your S-100 box. We will set the board up as a true S100 bus slave.  By programming the CPLD and with the additional circuitry on the board it can in fact run it as a bus master.  I will leave this arrangement to our more experienced users.

Here is a picture of the bare board:- 
  Bare V2 Board
Solder in all the required IC sockets, resistors, the transistor Q1, resistor arrays, capacitors, jumpers, and the 5V voltage regulator.  For the latter you can use (but I don't recommend) a 7805+heatsink approach (e.g.. Jameco # 924633, a L7805CV). Better to use a more modern switcher regulators such as the Pololu # 2850 (5V, 2.5A) or # PSU5a (5V 2.5A).  Do not add the LED's yet. Be sure you put the resistor arrays in with the correct orientation of pin 1. Make sure all the resistors are all connected to pin 1 and check their values before soldering (they are difficult to remove).  Insert all jumper arrays. Be sure and have pin 1 of the CPLD socket on the LHS. For prototype boards I typically use common Aluminum Electrolytic caps. For the final board I use the corresponding Tantalum caps.  Be sure you have the + side of each cap correct -- particular C1, C6, C5 & C2.  Note K10 can be used with a 3 pin jumper, but it's best to use a small switch (see the picture below).  Be sure you have the push button micro switch SW1 in its correct orientation. See the schematic. There is no need to add jumpers to P23 & P24 (under the CPU), these are there for debugging/testing purposes only.  If the board is to be used in slave mode only, you should in theory, not use the pull-up 1K resistors for the TMA lines (RR5).  However I find the 1K resistor load on each line with the 1K on the Z80 board is OK for its OC drivers to work fine. With the board configured as a bus master these lines must be pulled up so add RR5. You can use a jumper socket if you like.

Do NOT add sockets for U35,U31,U30,U37,U40,U39 & U28.  We will (later) solder these components directly to the board (under the CPU and ROMs), space is tight on this board.
For prototype boards I generally use "double swipe" IC sockets. For a critical board like this I prefer to use "Machine Tooled" IC sockets.  However they are more expensive and you have to be particularly careful not to bend the IC pins.  The two clock oscillators can have their own special sockets (e.g. Jameco #133006) but actually I find the "Machine Tooled" IC sockets make a better connection.  I in fact solder the 2MHz oscillator (P1) directly to the board since it will never be changed.
Place the board in the bus. Check the voltage to sockets on the board is about 5V by placing the board in your S-100 system using an extender board. With no load you will typically get 5.00V  (+/- 0.2V).  BTW, your system should boot and run correctly with its Z80 master CPU board. If not, you have a serious solder bridge somewhere on the board.  Before you do anything else with a magnifying glass go over every socket on the board and examine for proper solder joints. I like to "reheat" each joint just to be on the safe side. The silk screen/varnish on these boards us quite thick. It's easy not to have a good solder joint for the ground pins.  Double check.   Extra time here will save you hours later. 

Next insert all 10 LED's. Before soldering them in place ground one at a time pins 3,5,7,9 & 11 of U18, pin 13 of U32, on the CPLD side of resistor R7 & R20 and pin 2 of K10,  to be sure they are all OK.   (I always use a blue LED for D3 "Board Active"  in my systems).  Note the orientation of LED D1.  You can directly solder in the 2MHz Oscillator at this stage.   Leave it above the surface of the board in case there is a card guide issue.   Solder in both 2.2K Resistor networks (RP1 & RP2).  Check each pair of pins across the chip is 2.2K Ohms.
Here is a picture of the board at this stage.
  V2 Empty Board
First we will construct the basic circuit required for the master/slave S100 bus flip.
Please remember that for 3 or more pin jumpers, pin 1 is always the square pad.  It is not necessarily the one on the top, or LHS.  

First insert the CPLD in socket U15 taking care that pin 1 is in the center LHS.  Program this CPLD with the code provided at the bottom of this page.  If you are using a virgin CPLD you probably don't need to program it first but to be on the safe side you don't want input/output gate conflicts with a previously programed chip.  With no chips/jumpers on the board this is never an issue.

Next insert the second CPLD U25.  and program that one the same way.

The Z80 must boot up correctly with the two programmed CPLDs inserted.

We now need to add the input address line buffers (U30, U37 and U28)  as inputs to this U25 CPLD.  These chips must be soldered directly to the board (under the CPU and UART chips).  It is critical you are sure these buffers are OK. If possible pull chips from another working board, just to be sure.

While we are at it we may as well install the Interrupt Vector buffers U39 and U40 (74LS373's), and the "power on buffers" U31 & U35 (74LS244's).  All these chips should be known working chips before being soldered directly to the board. 

Install the "Power On Jumpers", P4 pins, 1-2 and 3-4. P3 pins, 5-6, 7-8, 8-10, 11-12, 13-14.   P20 pins, 1-2,  5-6,7-8.     P20 pin 3 to P4 pin 2. (See below and here for an explanation of these jumpers). It is absolutely essential that pins U39, U40, U31 & U35 are normally inactive.  Check the pins as shown below.
The board should now look like this:
  Step 2A

Add U3, U19, IC1, U21, U5, U34, U36 and U18.  Jumper P10 1-2 and K5 1-2. (Note pin 1 of K5 is on the RHS).  Add K14, 1-2 (assuming no Support Board currently).
In your Z80 monitor use the "O" command (or however in your system you pass control over to an S100 bus  slave device), check that that jumper pin P10 1-2 goes from LOW to HIGH.  Hit reset,  it should flip back to LOW. 
Add the 20MHz Oscillator P18. Jumper JP9. Add jumper K1 2-3 (bottom two pins).  Jumper P8 1-2 (top two pins) and K6 2-3 (right two pins).
Now with the "O" command the LED D1 "ROM Active" should light up as well as LED D3 "PDP Active". (The others are undefined).
A reset should turn off these LEDs.
Next we will add the UART serial interface to the board.
Add U2 (the MAX232N chip).  Add U6 (the UART). Add U5, U26, U10, U11, U9.  The add U1, U8 and U7.
Jumper K7 1-2 and K3 2-3.
Set the switch K10 (or jumper) 2-3. With power, the LED D9 should NOT light up.
When you press the button SW1 pin 9 of the CPU socket should go from low to high.

Assuming you will initially be using the DB9 serial socket J1, jumper P2 1-3, 2-4, 5-7 & 6-8. See the picture below.  BTW, the P2 connector is pin for pin compatible with the serial connector on our Serial I/O board so later you can hookup a ribbon cable internally in your system to a serial DB9 connector at  the back of your box.
Jumper K11 1-2 and K9 2-3.  Power up the board and check you are getting a ~156.24/16 KHz = 9765 baud if you have a frequency counter on pin 40 of the UART (U6).  At least check you are getting a continuous pulses with a logic probe on pin 40. 

To start, add a 3-6 MHz crystal to pins X2.   Then carefully add the J11 CPU chip.  The pins on this chip are delicate so be very careful inserting the chip into the two rows of sockets.  Double check you don't have any chips in backwards. Most of these CPU work well in the 10-12 MHz range but we will start off low. If difficulties below,  drop the frequency.

Next connect a serial connection to a TTY terminal on your PC to the top DB9 connector J1. 
There are many programs. I like "Absolute Telnet" but the free PuTTY or Tera Term ones are also excellent. 
The serial connection to this board must be (in the default mode USED here), 
9600 Baud, 8 data bits, 2 stop bits, and no parity.
If you use a USB to Serial connector/cable in most cases you need only specify the Baud rate and stop bits.

Power up your system and with the Z80 "O" command transfer control to this board.
You may see random characters on your TTY terminal.  Briefly press the SW1 button, you should see the J11 ODT Console signon prompt '@'. 
You may actually see the '@' signon with the 'O' command.
In every case however the SW1 button will present the ODT '@' prompt.

Since the is no RAM on the board at this time all you can do is display the CPU registers.
Type R0 followed by a '/' . You should see the current (random) value in the CPU's R0 register.
Typing further LF's (Crtrl j's), will cycle through all the CPU registers. 
Here is an example output:-
 Build Step 3e
You can change the (octal) values by entering a new value followed by a Ctl-J (LF) and go back and confirm the change(s).
Here is a picture of the board at this stage:
  Step 3
  Step 3A
It is absolutely essential you get the above diagnostic test working before going further. The ability to interact as described above is a fantastic advantage of this CPU chip.  Most of our other CPU boards require almost a complete build of the board before getting any life out of them.  Debugging such a non-functional board can be problematic.   There are few chips on the board at this stage. It should not be too hard to identify a problem.  Upon obtaining control of the bus. Pin 1 of U7 must go low. Pin 11 of U7 must be pulsing. Jumper K11 pin 2 must go from Low to High (INIT*, pin 33 of the CPU) after a hardware reset.  Pin 9 of the CPU (HALT*) should be Low (unless SW1 is pressed).

If you do not see the signon prompt, your first suspicion should be the serial connection to your PC.   Disconnect the serial connection and try a loop test or a connection to another serial port (ideally at 9600 baud). Be sure you have all the jumpers exactly as described and shown above. Check that pin 25 of the UART pulses low when you enter a CR from your PC.   BTW, if you have the SMB you can jumper this boards P10, 3-4,  and use TMA0* on that board for the PDP11 to get control of the bus.

Do not go forward until you get the above ODT signon test to work.

We will next (temporarily) add 16K of local RAM to the board to further test/flush out our circuit.  You could in fact skip this step since in the end we will be using only RAM on the S100 bus.  However I really recommend you go the extra mile.

Add two HM6264LP-10 (16KX8) static RAM chips (or their equivalent) to U12 & U13.
Jumper P11 1-2 (the jumper should be vertical on the LHS connecting Vcc to pin 26 of the RAM chips).
Jumper K2 2-3, K8 2-3 and K12 1-2.
Boot up the CPU with the usual "O" command.
You should be able to see and modify RAM starting at 0H in RAM.
Here is a picture of the board at this stage:-
  Build Step 4
Below we change the 16 bit words at 0-10H in RAM and then verify that we have done so.
Remember all values are in octal. All addresses must be on an even byte boundary.
 Build Step 4a
If you get this far you are well on your way to having a functional system.  The next step is to replace the onboard 16K of RAM with access to the S100 bus RAM. 
For this we need to add the S100 bus data buffers and for the first time call upon the CPLD to step in and handle RAM I/O requests.

First remove the onboard RAM chips U12 & U13. We will not need them any more. Remove Jumper P11.
For the (later) onboard ROMs jumper K2 1-2. Leave K8 2-3 for now.
Add U29, U32 and U33.  Add U24 (To prevent false interrupts).  Repeat the above ODT signon to display the CPU registers

Add U16 and U27 (the S100 bus status and control lines). 
Repeat the above ODT signon test from power up to display the CPU registers.

Add U17, U20, U22 and U23 (the data buffers to the S100 bus).   At this point all chips should be on the board except the two ROM sockets U13 & U12.
Add the 2MHz Clock jumper JP1. (Note this assumes your Z80/bus master hands over the 2Mhz clock to the current slave). This jumper is not clear on the silkscreen. It is just right of JP15.
Add the MWRT jumper JP2. (Note this assumes your Z80/bus master hands over the MWRT signal to the current slave).
Add JP14, JP15 and JP12 -- to be on the safe side.

Repeat the above RAM read/write test.
Go back to your Z80 and fill RAM 0-100H with say 01H. Then check with the PDP-J11 that you see these values (000401 octal). 
Here is a picture of what you should see for RAM at 0H.
 11 In RAM
Within the ODT change a few values to (say) 123 octal.
Go back to your Z80 and confirm the value has changed. You should see 53 00, 53 00, 53,00....
Remember within the ODT monitor all reads/writes are words on an even address boundary.
Here is a picture of the board at this stage:-
  Build Step 5
As we noted for the original PDP-11 CPU board, the J11 designates addresses 3F
E000h - 3FFFFFH as port IO's. We need to "translate them" to 8/16 bit ports 0000H-1FFFH on the S100 bus.  This is done in hardware and is completely transparent to the J-11 CPU.  The following circuit does the trick:-
 Port Address Lines
Unlike the original PDP11 CPU board the address line A12 is not altered so we get the full PDP11 port address range 0-1FFFH. Also there is an option within the CPLD U15 to cancel/modify this option with the S100_IO* signal.

At this point we start to utilize more of the code in the U25 CPLD.
We need to be especially careful with the onboard UART address lines.  For our original (V1) PDP11 CPU Board any an all address in the range 3F
FF70H to 3FFF76H went directly to the J11 for console/UART IO (and not act as ports on the S100 bus).  For this board there are two different situations:
If this boards UART is "acting alone" and only in status bit mode, than, as for the V1 board, all addresses in the range
3F1F70H to 3F1F76H  are blocked S100 bus access and go to/from the onboard UART.  If this board is working in bit and/or interrupt status modes with our PDP11 Support Board  then only the actual UART data ports 3F1F72H and  3F1F76H have blocked S100 bus access.  Which option is determined by the jumper K14 (in the middle of the board.  It is essential that this jumper is always in the correct position.  If it is not the V2 PDP11 CPU board will not be able to obtain console data and will hang.  So remember:-
  Support Board Jumper
I know this is going to be a source of error as people forget this requirement. The only way around this would be to have some signal value sensing from the Support Board coming across via the P12 connector -- perhaps in a later version of this CPLD code.  Here is the relevant code in the U25 CPLD:
!UART_ADDRESS = ((LA19_21 & LA18 & LA17 & LA16
                & LA15 & LA14 & LA13 & LA12 & LA11 & LA10 & LA9 & LA8
                & !LA7 & LA6 & LA5 & LA4 & !LA3 & LA1 & !SB_ACTIVE)      /* Ports 1F72, and 17F6 ONLY (Support board present) */
               # (LA19_21 & LA18 & LA17 & LA16
                & LA15 & LA14 & LA13 & LA12 & LA11 & LA10 & LA9 & LA8
                & !LA7 & LA6 & LA5 & LA4 & !LA3 & SB_ACTIVE));            /* Ports 1F70 to 17F6 (Support board absent) */

!UART_CS      = !UART_ADDRESS & !LBS_IO & !XFERII;                        /* UART is in range (No S100 bus ports allowed) */

UART_CS* is low the S100 bus buffers (U17, U20, U22 & U23) are inactive.

Make sure K1 is set to 1-2 (it should be from earlier above), set K7 2-3 and set K14 1-2.  Repeat the above RAM RD/WR test.

As described for the V1 PDP-11 CPU board, upon power up the CPU memory management facilities are not active.  Available RAM is in effect from 0H to DFFFH.   We will place the onboard ROMs at C000-DFFFH.  So any and all addresses in the range
C000H to DFFFH will go to the boards onboard ROM's and not input RAM data from the S100 bus.  Again we use the U25 CPLD to flag this situation as  ROM_ADDRESS*.  To be sure its working, use the ODT monitor command to examine RAM at 140000 (E000H).  Jumper K8 1-2. As you examine RAM in that range pin 2 of jumper K8 must pulse.   If not check the code in the U25 CPLD.

Burning the Onboard EEPROMS
Program two AT28C64 EEPROMs with the latest PDP11 monitor code available at the bottom of this page.  Be sure you correctly burn the High/Low bytes with your PROM programmer. Insert the 8KX8 EEPROMS (AT28C64). Make sure the High byte is in U13 and the Low byte is in U12. Jumper K8 from now on, should always be set 1-2.

Please note, versions V2 and later of the PDP_MON.MAC code allows you to use a High and Low 4K page of the 28C64 EEPROM.  This in effect doubles the capacity of code that can fit between C000H and DFFFH in the CPU's RAM space.  Programming these EEPROMs requires 4 files and is quite tricky.  See here.    Unless you are very comfortable with that process, during this build process start with the V1.5 version of the monitor which does not utilize this High/Low page feature.

just use the low page of the EEPROM to start with.  To do so, assemble and make a .bin file using:-
ROM_HIGH_PAGE: equ FALSE"  in the PDP_MON.MAC file. 

Do a "normal" Even/Odd EEPROM burn.  Note the High/Low ROM page feature requires K12 jumpered 2-3.  For the V1 or just low page option, use K12 1-2.

Reading RAM at 140000 (D000H) should show something like this, (if you use the V1.5 version of the monitor) :-   

This corresponds to the following code at the start of the PDP11 Monitor (V1.5).

140000 012706 137400          Start: MOV   #CPU_STACK,SP    ; Setup stack at BF00H (for now, below ROM ORG at C000H)
140004 012737 000340 177776          MOV   #&00E0,@#PSW     ; Block ALL Interrupts (Clear bits 7-5)
140012 012705 147713                 MOV   #Signon,R5       ; Point to Signon Message
140016 004767 006160                 JSR   PC,PrStr         ; Print string
140022 010605                        MOV   SP,R5            ; Show current SP
140024 004767 005736                 JSR   PC,PutWord_R5
140030 012705 150012                 MOV   #Signon1,R5      ; Point to Signon Message finish
140034 004767 006142                 JSR   PC,PrStr         ; Print string
140040 012705 146554          Loop1: MOV   #MainMenu,R5     ; Point to Main Menu
140044 004767 006132                 JSR   PC,PrStr         ; Print string

If the bytes are not the same as you have in your monitor code then the is probably an addressing problem with your EEPROMs. 
Note the start code for versions V2 or later is different -- see your PDP_MON.lst file printout.

If you are satisfied that you are reading your ROMs correctly use
140000G to transfer CPU control to your onboard ROM Monitor.  You should see something like this on your TTY terminal.
  ODT Signon

A PDP11 Recap.
As we noted for the original PDP11 CPU board, any and all addresses in the range (3F)E000H to (3F)FFFFH are understood to access I/O ports by the J11.  This board converts addresses in that range to the corresponding S100 bus I/O ports in the range 0 to 1FFFH. Only addresses 0H to (3F)DFFFH are available to RAM.  Further within the (3F)E000-(3F)FFFH block, (3F)FFE0H to (3F)FFE8H are "System Registers" (see below).  Further complicating matters when the J11 first powers up only the address range 0H to FFFFH is available (16 bits). The CPU internal memory management registers must be programed to access the 4MB (in 64K blocks).  So in startup mode accessible RAM is 0H to DFFFH. It is important to remember that any and all addresses in the range E000H to FFFFH are automatically translated to address (3F)E000h to (3)FFFFFH. In other words, with memory management inactive, if the address lines A15 & A14 are high then address lines A21-A14 are all high - no exceptions.  The J11 CPU lowers LBA_IO* for I/O access. We will generate a corresponding signal in the U25 CPLD called S100_IO* to activate ports on the S100 bus. So now you should also jumper K1 1-2 (it is on the top RHS of the board).  Repeat the above monitor signon display test.

So far we have been running the CPU at low speed with a 3-6MHz (see above).  We will now active the CPU's wait state capability by jumpering K9 1-2. While not normally used with our current high speed RAM boards, that jumper does allow us to utilize S100 bus wait states.  This can be seen if you use the monitor "D" command to display RAM and hit the SMB "Stop Button".

Next we need to have the CPU jump to the EEPROM and run the code from there in non-ODT mode. 
I will repeat the write-up on the J11 "Power Up" circuit we described for the V1 PDP11 board for clarity.

Normally upon power the CPU looks at the very initial values of its DAL0-DAL15 lines for startup information. On pages 8-7 to 8-8 of the PDP User Guide there is a description of a circuit that allows you to define where the CPU starts in its 64K RAM space.  Upon power up the CPU inputs the DAL 0-15 lines when a General Purpose Read  is placed on the AIO03-AIO0 lines (1110) and the Read code on DAL 0-7 is 000 or 002.  This is a single read/pulse.  The PDP interprets the 16 bit data as follows:-
 Power Up Bits

We incorporated the following circuit on the board to trap these situations:-
Here is the circuit:-
 Power Up Circuit
The U25 CPLD relevant code is:-

!reg0.d = !DAL0 & !DAL1 & !DAL2 & !DAL3 & !DAL4 & !DAL5 & !DAL6 & !DAL7
        # !DAL0 & DAL1 & !DAL2 & !DAL3 & !DAL4 & !DAL5 & !DAL6 & !DAL7; = !MASTER_RESET; = ALE;

!POWER_UP = !reg0 & LAIO3 & LAIO2 & LAIO1 & !LAIO0 & !BUFCTL;

We use the above CPLD code to provide the one time only, initial pulse to the two 74LS244's. The input values are determined by the jumpers P3, P4 and P19, P20. Way back at the start we jumpered P20 & P19 to always power up in ODT mode. In particular  P20 pin 3 to P19 pin 2.  We will now set P20 Pin 2-3.   If both the DAL1 & DAL 2 lines are high the CPU on power up will bypass the ODT console mode and directly jump to the address boundary defined by DAL15-9. This should always happen UNLESS the J11 HALT (pin 9) is high.   Depending on the jumper/switch K10 the PDP monitor will either input/output through  the UART (LED D9 off) or to the S100 Bus Console-IO board (LED D9 on).   With the D9 LED on, its very exciting and rewarding for the first time to see a display like this:-
  Monitor Signon
Please read about the PDP11 Monitor commands here.  Remember if you utilize the High/Low Page ROM options jumper K12 2-3.

You now have the PDP V2 board running essentially as the original "V1" board.

Remember if you are in "S100 Bus" mode and you press the pushbutton SW1 you will always force the PDP11 into ODT mode where output will only appear via the onboard UART to your TTY terminal.  If the serial connection is not in place the board will appear hung.

The next step is to implement PDP11 style interrupt processing.  This is where this board differs considerably from the original V1 PDP11 board. Before you do this you need to carefully read the write-up on the PDP11 Support board and build it. We will do the PDP11 interrupt testing of this board also on the PDP11 Support Board page.

You can at this stage however experiment with CPU speeds. The one thing I have noticed is that while the CPU is not real sensitive to clock speed, it is to the actual waveform going into its pins 36 & 37.  They must be 'clean'.  Sub-quality crystals, or, their connection really cause problems. In my two systems, the board seems to run rock solid with a S100 Bus Phi clock signal of 10MHz.  Note this is an active terminated IEE-696 S100 bus. Your mileage may vary.  

The PDP-11 Board Jumper Table
There are a fair number of jumpers on this CPU board and they need to be set carefully.  To run the board as a bus slave (with a Z80 master)  here is a typical jumper setup:-
Jumper   Function 
JP2Normally closed. Generate the S100 bus MWRT signal on this board when it is active.
JP1Normally closed. Generate the S100 bus 2MHz Clock signal on this board when it is active.
P11 Jumpers to accommodate RAM or ROM chips. For RAM J11 1-2. For EEPROM's leave open.
JP4,JP5, JP6,JP7Normally all open unless the board is a bus master.
JP13,JP15Normally closed to utilize the S100 bus Phantom Line. Normally no need for JP15
K2 & K8RAM/ROM OE* & WR* signals. For RAM jumper both 2-3. For EEPROM jumper both 1-2.
K1Normally 1-2
K9 Normally 2-3 during board for testing/assembly. Allow S100 bus wait states with 1-2
K7UART Select, Set 1-2 for core circuit testing. Normally 2-3
K5For slave mode 1-2
JP9Jumper after the CPLD is programmed
K6,JP12Set 2-3 and jumper JP12
P8Set 1-2 and jumper JP13
P9 or P17CPLD JTAG programming socket. For Rockfield Research 1508 programmer use P5. Pin 1 is bottom left.
P10S100 Bus TMA line to activate board. Normally 1-2 (also jumper 3-4) . Assuming TMA0 to activate board.
K4Currently unused. Set aside to configure Master/Slave configurations in CPLD code
P15Inputs from S100 bus Interrupt vectors. See PDP11 Support Board
K10/SwitchThis can be a mini-switch or jumper to determine where the PDP_MON monitor data I/O is sent
P2This a serial port connector for the UART with a pinout like our Serial board. If the DB9 socket is used it must be jumpered as described above.
K14VIP Jumper. Used to determine if PDP11 Support Board is present.  If so, jumper 2-3.
K12Used to select Upper/Lower EEPROM. For debugging use 1-2. For page management use 2-3.
P22. P25These jumpers allow the onboard UART status signals to reach the PDP11 Support Board. Normally jumpered.
K13, JP20, JP19Unused jumpers to S100 bus unused lines.
P12Overhead ribbon cable connector to PDP11 Support Board.
SW1 Pushbutton switch to force PDP11 into HALT/ODT mode.
K12 For the High/Low ROM page option 2-3.  Initially start with 1-2.

PDP-11 S100 Board Parts
The PDP-11 chip is not available from most vendors.  It is found on eBay -- either as the chip alone see here or it can be pulled from Digital boards.   It is almost always socketed on those boards. A typical eBay price is $100/chip. Most of the other components are common. I usually get them from obtained from Anchor Electronics and Jameco.  The 1508 CPLD's (#556-ATF1508AS-10JU84) from Mouser.

PDP-11 CPU Board  Bugs & Notes.
So far no bugs have been reported for this board.  To my amazement this board runs absolutly rock solid in both my S100 bus systems with a 20 MHz crystal putting a 20MHz Phi on the bus!  Note, both systems have terminated buses -- your milage may vary.

Realizing that a number of people might want to utilize a board like this a "group purchases" will be  opened on Google Groups S100Computers Forum.   Join the group and follow the progress.  Boards are $18/board.  Do not e-mail me directly for any requests.

Finally please note, currently (Dec. 2017),   the PDP-11 V2 monitor is being actively updated.  Please go to the PDP-11 Software page for the most current update.
The links below will contain the most recent schematic of this board.
Note, it may change over time and some IC part or pin numbers may not correlate exactly with the text in the article above.

DC-11 User Guide
                                                                     ( 2/13/2017)
PDP-11 Programmers Card                                                   ( 4/5/2017)
AsmPDP Assembler (Zip File)                           ( 4/5/2017)     (From 

PDP.MONITOR V1.5 (MAC File)                                            (No ROM pages)                               
PDP.MONITOR V1.5 (Zip File)                                         (No ROM Pages)       

PDP.MONITOR V2.0 (MAC File)                           (V2.0 12/5/2017                                 
PDP.MONITOR V2.0 (Zip File)                           (V2.0 12/5/2017)        

PDP11V2.5f Schematic.pdf                             
 (V2.5f  12/4/2917)
V2 PDP-11 Board KiCAD.Zip
                                (V2.5f  12/4/2017)
V2 PDP11 CPU Gerber Files Folder                      (V2.5f  12/4/2017)                                
PDPMAIN1.PLD                                               (V2.5f  12/4/2017) 
PDPMAIN2.PLD                                               (V2.5f  12/4/2017)    
V2 PDP-11 BOM                                               (V2.5f  12/4/2017)                                       

Other pages describing my S-100 hardware and software.
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This page was last modified on 12/13/2017