S100 Computers - PDP11 Support Board

The PDP11 S100 Bus Support Board.

This is a very specialized board for our PDP11 S100 bus V2 CPU Board. The aim of this board is to as far as possible emulate certain hardware features of the PDP11 series minicomputers such that Digital OS/Software of the era (1770's) will not know it is not running in such a system. This is clearly a difficult task since such systems utilized a 16 bit bus, have no dedicated instructions for I/O to hardware ports and an interrupt process/structure that is different from say a typical Intel style interrupt.   Fortunately there are excellent manuals available that explain in detail the software and hardware of the PDP11 series of minicomputers.

This board is intended to work hand in hand with the V2 PDP11 CPU board. It will not work with the original "V1" PDP11 CPU board. The critical prioritized interrupt request and acknowledge lines are connected between the two boards using a 6 pin ribbon cable at the top of both boards. It is essential that you become familiar with everything about the V2 PDP11 CPU board before building and using this "daughter" board. The major functions on this board are:-

1.    The two UARTs on this board can process interrupts compatible with Digital software for a DL-11 Serial board interface.
2.    Multiple S100 bus (and this board's interrupts), are processed and prioritized (Digital style) by a circuit on this board.
3.    Pending interrupts are cleared in the correct order by a circuit on this board as Digital software expects them.
4.    There is a parallel printer port circuit on board to emulate a LP11 Digital Parallel Printer interface board.
5.    Numerous LEDs are onboard to indicate active functions.
6.    All port selection (16 bits), and signal processing are programmed into one onboard 1508 CPLD

Please note that I do not yet have a running tape controller board and a running Digital OS, so the above should currently best regarded as goals!

Also, this board can be used with any S100 bus CPU. While it is built for some of the unique requirements of the PDP11 system it is in fact a general purpose dual RS-232 serial port and parallel port board -- each with their own status bits and if required bus interrupts. For a typical 8 bit CPU (e.g. a Z80), one would just need to reprogram the onboard I/O port range.

PDP11 Interrupt Processing.
The PDP11 handles external hardware interrupts quite different from say the Intel 86 family of CPU's. The problem we run into with our S100 bus is the generation of the INTA signal. This is the S100 bus signal that tells S100 bus boards that an interrupt has been acknowledged by the (current) bus master. We had a similar issue with our Motorola 68030 board, we cannot use the Intel 8259A Interrupt controller on our MSDOS Support board because it requires two back to back INTA signals before it places the highest priority interrupt vector on the S100 bus data lines. If you wish to utilize an 8259A with this board you will have to generate two back to back INTA S100 bus signals while holding the PDP11 CPU in a wait state. I have not explored this but I think it is doable with code in the CPLD.   Another approach would be to utilize a more programmable interrupt controller such as the AMD 9519 on a custom board.

Instead, we will try and do exactly what the Digital PDP11 minicomputers do, we will, externally of the CPU, prioritized our interrupts in hardware, have the "current winner" trigger one of the J11 CPU pins (IRQ0-IRQ3), and depending upon its value isolate the boards S100 data bus and force a 16 bit "interrupt vector" locally on to the CPU's DAL0-LAL15 lines so it jumps to a specific interrupt routine in RAM. When done control is returned back to the S100 data bus. Sounds easy! Right. It turns out to be more difficult than you would think. A simple approach would be to use a Digital M78020 (or M7821) Interrupt Controller chip. Unfortunately this chip is extremely rare and would have to be pulled from a Unibus Board. We will emulate the chip ourselves.

Below is the core of the PDP11 Support board interrupt prioritization circuit I used. Lets first at the interrupts generated by the onboard U58 UART, the "TU58 UART" which uses 4 I/O ports 1F40H-1F47H.

Two separate interrupts are generated by the TU58 UART. One when a character is received and ready to be read, TU58_RCV_READY going HIGH. The second when the UARTs transmit buffer is empty and is ready to send another character (if one is available) TU58_XMT_READY goes HIGH. It's up to the OS software to decide what to do when these interrupts are triggered.   Remember however, that contrary to some other computer systems, the TU_XMT_READY interrupt is trigger only once the transmit buffer turns empty NOT when the character has been sent. So to send a character via the UART you must first check that the buffer is empty flag is set in software.

The Interrupt generating hardware associated with this UART is shown here:-

In the PDP11 Digital Unibus system, the two TU58 UART interrupts must first be activated in software by setting bit 6 of ports FF40H and FF44H High, (the TU58 Status Registers) . This we do by setting the U27A Flip Flop (FF) for RCV (and U33A for XMT). Then (and only then), can the U27B FF be clocked by the UART TU58_RCV_READY (or U33B by TU58_XMT_READY) signals. The CPU, at any time, can read this "TU58 activated bit" by inputting from U29 or U32 (bit 6).

Let us follow the TU58_RCV_INT. It travels from U23C pin 8 to pin 3 of P2. See here:

Latch Enable of U53 pin 11 is normally high, so depending on our "Interrupt prioritization" jumpers on P2, it will reach the inputs or the priority encoder chip U20 a 74LS148. This chip will output a multiplexed 3 bit priority code (S0,S1,S2).    These travel over our Support board top ribbon cable connector P8 to our V2 CPU board where they reach its U25 CPLD.   Lets leave them there for a moment. Also whenever any input pin of our encoder goes low to the 74LS148 its pin 14 will trigger an interrupt on one of the S100 bus lines (via P9). We will use the S100 bus VI0* bus line (P9 jumpered 1-2). This will get to the V2 PDP11 CPU board and trigger the CPU's IRQ0 line (pin 10).

When the V2 PDP11 CPU is ready to process an interrupt arriving over the S100 bus interrupt lines, it will issue an interrupt acknowledge by the following unique code:-

bsINTA = LAIO3 & LAIO2 & !LAIO1 & LAIO0;                           /* Instruction INTA vector read request from CPU */

Note, this is the only time the CPU issues this unique combination of LAIO-LAIO3 values.    We use this value to raise the S100 bus sINTA line (pin 96) with code in the CPU Board U15 CPLD.   Over on our Support board this raise sINTA line latches the current values into our 74LS373 and thus fixes the current value in the priority encoder and the S0, S1 & S3 lines of U20.

At the same time, back on the CPU board, the U25 CPLD seeing this same sINTA and reading the values of S0, S1 and S2 (now fixed), forces the relevant interrupt vector RAM location on to the DAL0-DAL15 lines of the CPU. This is done with U39 and U40 on the CPU board. During this brief time the CPU data lines are isolated from their S100 bus buffers (bsINTA will be high in the relevant U15 CPLD functions).

The heart of the interrupt prioritizing and processing resides within the V2 CPU board U25 CPLD. Here is a very simple example.

FIELD INT_VEC = [VEC_DAL7,VEC_DAL6,VEC_DAL5,VEC_DAL4,VEC_DAL3,VEC_DAL2,VEC_DAL1,VEC_DAL0];
FIELD INT_CODE = [S2,S1,S0];

!VEC_OE = LAIO3 & LAIO2 & !LAIO1 & LAIO0 & !BUFCTL;                 /* CPU instruction INTA vector (1101) read request */

TABLE INT_CODE => INT_VEC {
               'b'000 => 'h'38; 'b'001 => 'h'38; 'b'010 => 'h'38;   /* S2,S1,S0 => Active LOW */
               'b'011 => 'h'38; 'b'100 => 'h'38; 'b'101 => 'h'38;
               'b'110 => 'h'30; 'b'111 => 'h'38;
               }

In the above simple example, if S0 is low and S1 & S2 are high the CPU will load the interrupt vector routine at 30H in RAM. If 110 is not the S0-S2 value the default routine at 38H is called. In each case the location contains only two 16 bit values. The first being the start address of the actual vector code the CPU will jump to. The second is the PSW the CPU will use when starting this routine. In all cases the interrupt routine will utilize an IRET instruction restoring the previous PSW and PC when finished. Here is a very simple example of a routine to print a character received from the TU80 UART.

TU58_RCV_Routine0:                     ; TU58 RCV Int will arrive here (location obtained from 30H in RAM)
               MOV R0,-(SP)            : Save the Stack
               JSR PC,TU58_UART_IN     ; Get Character at UART to R0
               JSR PC,CONSOLE_OUT      ; Just dump it on console (Later can use buffers etc.
               MOV (SP)+,R0            ; Return the Stack
               RTI

Which of the CPU Interrupt lines (IRQ0-IRQ3) to use? In most Digital PDP systems all UARTs use the same CPU interrupt line, IRQ0.   That was actually the default interrupt for all digital OS. (Most mass storage devices like the RK05, RL02 or RM03 disks etc. used IRQ1).

In Digital OS software, both TU58_RCV_READY* and TU58_XMT_READY* trigger IRQ0. Within the response vector process as described above, the routine will jump to a routine in RAM based on the above S0, S1 & S2 values. If the S0,S1,S2 value corresponds to a received interrupt from the TU58 UART, that routine will read the character available on the UART and deal with it. It will then clear that interrupt line via CLR1* (U9D) and do an IRET. If the S0,S1,S2 value corresponds to a transmit buffer empty interrupt from the TU58 UART it will let the monitor/OS know -- usually by setting a flag in RAM. It will then clear that interrupt line via CLR3* (U11B) and do an IRET.

Remember there are four 16 bit wide I/O ports involved for the above UART U58.

TU58 UART Data In Status Port 1F40H
TU58 UART 8 bit Data In Port 1F42H
TU58 UART Data Out Status Port 1F44H
TU58 UART 8 bit Data Out Port 1F46H

Keep in mind the CPU on the V2 CPU board actually sees these ports as 3FFF40-3FFF46. So if you a using the Monitor to output a Byte or Word to one of these ports they must be in the range FF40H -FF47H. It is essential you understand all of the above if you wish to understand the interrupt circuit/software on these two boards. Please re-read the above summary several times if necessary until you get it.

A Printer Port
There was still some room on this board to add a printer port interface. It's essentially half a UART in terms of status circuitry. Here is the core schematic.

Since most people probably will not be using an old Digital DECprinter I (LA180), I have added a number of jumper options so the parallel port can work with other printers. Again the interface used a 16 bit wide status port (U6). Bit 15 of that port 1F4CH (3FF4CH) is an error checking bit. While the Digital OS software utilizes a strictly interrupt driven approach -- which I also allow, I have squeezed in a status bit approach option utilizing bits 8 and 9 of port 1F4DH (3FF4DH) for a quick and dirty software status driven driver approach. BTW the printer connector (P14) has exactly the same pinout as our MSDOS Support board connector so the same cable can be used for either board if necessary.

Step By Step Building the PDP11 Support Board
The build instructions are fairly simple for this board but because it is a complex board building it should not be rushed. As always, first examine the bare board carefully for scratches or damaged traces, use a magnifying glass if need be. A broken trace is almost impossible to detect by eye on a completed board. Please note some of the pictures below are with the earlier prototype board. It's identical to this final version above except for the repositioning of a of a few jumpers and two extra IC's.

Build the board up in functional steps. Avoid the temptation of adding everything at once and popping it into your S-100 box.
Here is a picture of the bare board:-

Solder in all the required IC sockets, resistors, resistor arrays, capacitors, jumpers, and the 5V voltage regulator. For the latter you can use (but I don't recommend) a 7805+heatsink approach (e.g.. Jameco # 924633, a L7805CV). Better to use a more modern switcher regulators such as the Pololu # 2850 (5V, 2.5A) or EzSBC.com # PSU5a (5V 2.5A). Be sure you put the resistor arrays in with the correct orientation of pin 1. Check their values before soldering (they are difficult to remove). Insert all jumper arrays. Be sure and have pin 1 of the CPLD socket on the LHS. For prototype boards I typically use common Aluminum Electrolytic caps. For the final board I use the corresponding Tantalum caps. Be sure to add the two diodes in their correct orientation (the black ring pointing up). Before adding anything check the voltage regulator supplies 5V +/- 0.1 Volts. Check the LEDs are working by grounding the appropriate pins of U12 with a probe (3,5,7...).

Here is a picture of the board at this stage:-

Insert the CPLD (U8) and program it with the code supplied at the bottom of this page.

We will assume here that the S100 bus TMA0* line is used to activate the V2 PDP11 CPU, so jumper P19 1-2. (Later you can change the TMA line for the PDP11 CPU and this board if you have other slave CPUs in the bus.

The TU58 UART
First we will add the boards UART circuit (U58). This is a completely independent serial connection -- independent of the UART serial connection on the V2 PDP11 CPU board. It would correspond to a Digital TU58 board.   This UART will be "interrupt driven" as is the serial interface on the Digital TU58 board. It's primary use will be to interface with a Digital tape drive.

First add the Baud rate generator U11 and (assuming 9600 Baud), jumper P3 5-6 (third row from the RHS). Jumper P4 1-2 & 3-4.
Insert U58, U52, U21, U16 & U38. Jumper the P11 serial port the same way as we did for the CPU board, pins 1-3, 2-4, 5-7 & 6-8.
This assumes for now we will use the RS232 socket J2.
For P12 jumper the bottom 3 pairs of jumpers, RHS. The is no connection to the P15 row of pins in our default configuration.

Add U12. Add U40, U41, U43, U19, U36, U1, U46, U13, U15 and U25.
Add U29, U32. Add U27, U28, U23, U33, U5 and U34. Add U4.
Jumper K5 1-2. Hookup the J2 serial port to a serial/USB port on your PC. Launch your TTY terminal as you did for the CPU board UART. (9600 Baud, NP, 2 stop bits).
On your V2 PDP11 CPU board make sure you have jumpered P10 2-3 (irrespective of if you use the onboard CPLD code or the SMB to select TMA0*).

Boot up the V2 PDP11 CPU board.
Go to the "W" menu and use the '0' option to send the '3' character to the TTY terminal 60 times. A line of '3's should appear on your TTY terminal. The Board Select LED (D8) should briefly flash. The other LED's are undefined at the moment - normally they are all off.

Next connect a serial connection to a TTY terminal on your PC to the top DB9 connector J2. There are many programs. I like "Absolute Telnet" but the free PuTTY or Tera Term ones are also excellent. The serial connection to this board must be (in the default mode here), 9600 baud, 8 data bits, 2 stop bits, and no parity. Note it's often easier to use a USB to Serial Adaptor to connect to your PC. These units only require the baud rate and stop bits for configuration. In any event bring up the PDP11 Monitor and use the "W" command:-

Determine that you can get the first 3 menu items working reliably. Menu "C" should allow you to type directly on your PC TTY from your S100 Bus keyboard.   Again do not go further until you get this to work reliably. If you have problems, try sending continuous '3's to the FF46H port (O Command, Menu#3). Track the signals across the board.

Its important to remember what these two LEDs D5 & D6 signify. Probably not what you think.
When TU58_RCV_LED is on it signifies that the UART is "activated/capable" of received interrupts when a character arrives on its IN port (FF42H).
When TU58_XMT_LED is on it signifies that the UART is "activated/capable" of receiving interrupts to signify it is busy sending a character out on its OUT port (FF46H).
In the above tests the will not be ON because we have not activated the UART interrupt circuits.

Next we will setup this same UART to be "interrupt driven". Please re-read the theory on how interrupts are done on this board before proceeding.
Add U53, U20, U37 & U5.
Construct a 6 line ribbon cable connector between the top P13 connector pins on the V2 CPU board and P8 on this board. Initially use a long 10" ribbon cable so either board can be tested in in a bus extender card. For the final board set, the ribbon cable can be very short.   Be absolutely sure you have the pin connections for this cable correct. Check Pin 1 goes to Pin 1, 2 to 2... etc.   Here is a picture:

On your V2 PDP11 CPU board we will use the S100 bus VI0* interrupt line. So on that board jumper P15 1-2. On this board, jumper P9 1-2.
Lets first concentrate on interrupts received by the TU58 UART.
For the RCV interrupt jumper P2 3-4 (Interrupt Priority) and P10 3-4 (Interrupt CLR1*).
Make sure you have the 6 pin ribbon cable connection between the PDP11 CPU board and this board connected.
Next boot your system, bring up the PDP11 Monitor.
Go again to the "W" menu and use the 'G' option to receive characters from your TTY terminal.
You should see a display like this on your S100 bus console screen like this:

If you get this far you are well on your way to having a functional PDP11 Support board.

Understand what is happening here. The interrupt generated by the raised UART pin 19 and is triggering an interrupt signal at pin 3 of P2. It leads to a S0,S1,S2 (a three bit encoded signal) on P8. This travels to the V2 CPU board U25 CPLD. At the same time a VI0* S100 bus interrupt travels from P9 pin 2 to the V2 PDP11 CPU board P15 pin 1 which travels to the PDP11 IRQ0 pin. The PDP CPU recognizes the interrupt, issues an S100 bus sINTA and signal jumps to the RAM location determined by the values of S0,S1 and S2, does whatever is required and returns to its normal programming. The S100 sINTA signal is picked up by this board and sends out a CLR1* signal to the TU58 Flip Flop (U27) clearing that particular interrupt.

The nice thing about this board is that all the steps above are "visible" in the form of discrete TTL IC's. On earlier prototype boards I have much of the above within the U8 CPLD.   Since there was not enough space even then, for any further functionality to this board I opted use the extra board space to simplify the design for debugging. If you do not get the above test to work check each step in the above process with a logic probe. Do not go further until you get these things working. If need be use the diagnostic LED (D1), within the U8 CPLD to help.

For this RCV interrupt vector, look in particular at U20.   Pins 6 & 7 should pulse low, pin 9 should stay high (this is the S0,S1,S2 code 001). BTW, there is nothing particular special in the CPLD code for this board. Its sole function is to decode the designated ports and activate the relevant buffers.
Here is the port decoding for the TU58 UART ports.

!TU58_UART_ADDRESS = !bA15 & !bA14 & !bA13 & bA12                                            /*(3F)F -> 01 */
                    & bA11 & bA10 & bA9 & bA8 /* F -> F */
                    & !bA7 & bA6 & !bA5 & !bA4 & !bA3 & (bsOUT # bsINP) & !TMAx & !bpSYNC;   /* 40 -47 */

TU58_RCV_STATUS_WRITE = !TU58_UART_ADDRESS & !bA2 & !bA1 & !bA0 & bsOUT & !DELAYED_bpWR;     /* BYTE/WORD 1F40H */

!TU58_RCV_STATUS_READ = !TU58_UART_ADDRESS & !bA2 & !bA1 & !bA0 & bsINP & bpDBIN;            /* BYTE/WORD 1F40H */
!TU58_RCV_STATUS_HIGH_READ = !TU58_UART_ADDRESS & !bA2 & !bA1 & bA0 & bsINP & bpDBIN;        /* BYTE 1F41H */

!TU58_DRR = !TU58_UART_ADDRESS & !bA2 & bA1 & !bA0 & bsINP & bpDBIN;                         /* [DATA] BYTE/WORD 1F42H */

!TU58_HIGH_DRR = ((!TU58_UART_ADDRESS & !bA2 & bA1 & bA0 & bsXTRQ & bsINP & bpDBIN)          /* BYTE 1F43H */
               # (!TU58_UART_ADDRESS & !bA2 & bA1 & !bA0 & !bsXTRQ & bsINP & bpDBIN));      /* WORD 1F42H */

TU58_XMT_STATUS_WRITE = !TU58_UART_ADDRESS & bA2 & !bA1 & !bA0 & bsOUT & !bpWR;              /* BYTE/WORD 1F44H */

!TU58_XMT_STATUS_READ = !TU58_UART_ADDRESS & bA2 & !bA1 & !bA0 & bsINP & bpDBIN;             /* LOW BYTE or WORD READ 1F44H */

!TU58_TBRL = !TU58_UART_ADDRESS & bA2 & bA1 & !bA0 & bsOUT & !bpWR;                          /* [DATA] BYTE/WORD 1F46H */

Next lets activate the TU58 XMT interrupt. Jumper P2 7-8 and P10 7-8.
Next boot your system, bring up the PDP11 Monitor.
Go again to the "W" menu and use the 'H' option to transmit characters from your TTY terminal.
You should see a display like this on your S100 bus console screen like this:

The Printer Port Circuit
Please re-read the above description of the Printer Port circuit. There are a number of possible handshake signal possibilities for printers. It should be possible to interface most with this board. I will use as an example a HP LaserJet 1012 printer. Like most LaserJet printers it prints a page at a time. So if you send only a few characters you have to "flush the page" to actually see the printout. For the HP LaserJet 1012 the command to do this is the ASCII "Form Feed" character (0CH).

Insert U6, U2, U31 and U30. Jumper K2 2-3.
The parallel printer port is pin for pin compatible with the old IBM PC parallel printer port. In particular the strobe* signal is on pin 1. Data is on pins 2,5,7,9,11,13, 15 and 17.
Again boot your system, bring up the PDP11 Monitor.
Go again to the "W" menu and use the 'K' option to print a test string on your LP11 printer port. The Monitor command includes the "Flush page" FF character.
You should see the following printout.

You should see a printout like this:

Please note this very simple test routine simply uses the Support Board parallel (P14) at port 1F4EH and strobes each character on port 1F4FH (P14 pin 1). No interrupts are utilized. A proper routine would either look at the busy bits on port FF4DH (U6) or utilize interrupts.

There are numerous ways an interrupt could be utilized with this printer port. The interrupt enable circuit (U33 etc.) is exactly as described above for the TU58 UART. The user can experiment with a number of arrangements utilizing either the status bits on the Printer Status High Byte port (U6) FF4DH.

As a simple example I use the ACK* signal sent back from most printers as they receive a character. By jumpering P27 3-4 the HIGH ACK* pulse will feed into U28C and clock the U30D FF generating an interrupt on U36 pin 10. This goes to P2 Pin 15-16 and leads to a S0,S1,S2 code of 111. The V2 CPU board with this code in the U25 CPLD activates an Interrupt vector at 80H in RAM. The interrupt is cleared as described above for the UARTs using in this case the P10 15-16 jumper. Please see the PDP11 Monitor code "TestPrinterInt:" for more information.
Here is a typical Console Output using the "W" Menu and the "L" command:

THE CONSOLE ODT UART
As we have seen, the PDP11 CPU board and the more recent V2 PDP11 CPU board have their own 6502 UART which acts as the monitor/Console IO interface for the PDP11 CPU. It just so happens the 6502 behaves exactly the way the PDP11 ODT monitor expects the status/data port arrangements to be. This makes life very simple interfacing the CPU to the outside world.   The 4 UART ports (Data/Status, In/Out) were hardware set to FF70H-FF76H within the CPU. All of this is fine for using the UART to run the ODT monitor or in fact our own PDP11 ROM based Monitor.

However there is one major problem when we come to running the Console IO with Digital OS software, the UART does not trigger interrupts and so cannot be interrupt driven as for example we did above with the above TU58 UART.   There simply was not enough room on an S100 CPU board to incorporate an Console IO interrupt circuit and associated buffers on the board.

We need to have an interrupt driven console IO UART to work with "Out of the Box" Digital OS software. After trying a few options such as sharing the CPU UART with circuits on the Support Board, in the end I decided the easiest approach is to duplicate the ODT Console UART completely on this board exactly as we did for the above TU58 UART -- just with an address range FF70-FF76H.

This makes things a little complicated however, because I use an unused bit 0 of the CPU Board ODT UART status out port to read the polarity of an input from that boards switch K10. U5C (a 74LS126) feeds into the CPU's DAL0 line when we call XMT_STATUS. If it is high all ROM Monitor console I/O goes to the ODT UART. If it is low all console I/O goes to the S100 Bus console, (usually our Propeller driven Console IO Board). If the new location of the ODT UART is on the Support Board this input would be missing.   We need to assign a new port for the CPU board UART and use the switch settings for that port. We will reassign the CPU Board UART four ports to FF10-FF16 when the Supports Board ODT UART is active.

So, when, (and only when), the Support Board is present the UART on the CPU board UART will get a new address range (FF10-FF16). When it is absent it will have the normal FF70-FF76 ports range. We do this in software with the following code in the U25 CPLD on the V2 CPU Board:-

!UART_ADDRESS = ((LA21_19 & LA18_16                                     /* Always 3F */
                & LA15 & LA14 & LA13 & LA12 & LA11 & LA10 & LA9 & LA8   /* Note address lines before U29 (FF10-FF16) */
                & !LA7 & !LA6 & !LA5 & LA4 & !LA3 & SB_ACTIVE)           /* All 4 U6 ODT UART Ports do not go to the S100 bus */
                                                                         /* The ODT UART (FF10-FF16) is on the Support Board.*/

               # (LA21_19 & LA18_16                                      /* Always 3F */
               & LA15 & LA14 & LA13 & LA12 & LA11 & LA10 & LA9 & LA8    /* Note address lines before U29 (FF70-FF76) */
               & !LA7 & LA6 & LA5 & LA4 & !LA3 & !SB_ACTIVE));           /* All 4 U6 ODT UART Ports do NOT go to the S100 bus */
                                                                         /* The ODT UART (FF70-FF76) is on this Board

!UART_ADDRESS is fed into the U15 CPLD on the V2 CPU board, where if required by the CPU, the appropriate Console UART is activated, (UART_CS*, K7).
Within the ROM based monitor any console IO first checks where the I/O should go. Here is an example of the main CONSOLE_OUT Routine:

Set_CONSOLE_IO:                                 ; Set FLAG in RAM to decide where Console IO is directed.
      CMPB    #&FF,@#DEBUG_CONOUT_STAT          ; See if Port FF14 is present. (Will be FF if no Support Board present)
      BEQ     NO_SBoard
      BITB    #BIT0,@#DEBUG_CONOUT_STAT         ; See if input comes from the S100 Bus (Support Board present)
      BEQ     SET_S100_CONSOLE
SET_ODT_CONSOLE:
      MOV     #&FFFF,@#CONSOLE_IO_FLAG          ;FFFF = ALL CONSOLE IO TO ODT UART. ANYTHING ELSE THEN SEND TO S100 CONSOLE
      RTS     PC
SET_S100_CONSOLE:
      MOV     #&0000,@#CONSOLE_IO_FLAG          ; FFFF = ALL CONSOLE IO TO ODT UART. ANYTHING ELSE THEN SEND TO S100 CONSOLE
      RTS     PC                                ; Note R0 contains ASCII character (as a Byte)
NO_SBoard:
      BITB    #BIT0,@#ODT_CONOUT_STAT           ; Input comes from the CPU Board UART (No Support Board Present)
      BEQ     SET_S100_CONSOLE
      BR      SET_ODT_CONSOLE

We use a RAM location CONSOLE_IO_FLAG (at BFFEH) that contains a flag to define where all Console IO is directed. There are other ways it could be done including reading both ports each time during all Console IO or the IOBYTE port on the SMB.   A RAM based flag is the fastest and most efficient.

The critical jumper on the V2 PDP11 CPU board is K14. This jumper determines the status of SB_ACTIVE. So we will then have 3 UARTs on this dual board set. Remember however the UART on the CPU board is only handshake driven. An excellent use for such a UART is a debug monitor that issues information transparent to the main monitor Console IO.

Lets get started. First we need to inactivate the Console IO UART (U6) on the V2 CPU board.

We will now jumper K14 1-2. Remember in this configuration there is no valid ODT Console on the CPU board. Setting the ODT/S100 switch to ODT mode and using the serial TTY terminal with the CPU board UART will cause it to appear as if the CPU has hung. Of course output to the S100 bus Console is fine.
Remember all ODT Console IO from the V2 PDP11 CPU board will be inactive if K14 is jumpered 1-2 and the Support board is not present.
The CPU board will appear hung. (The S100 bus Console IO will be active however). To use the V2 CPU board alone, always jumper K14 2-3.

Add the second UART U10. Add U3, U17, U18, U26, U22 & U24 and U7.
For now lets start with the default 9600 baud, 8 data bits, 2 stop bits, and no parity arrangement, jumpers as we did for U58. However the is a little complication for 9600 baud. There are only 3 rows of jumpers so you need to wire-wrap the three jumpers as shown here. Later we will be using higher speeds so this will not be a problem.

Jumper the P16 serial port the same way as we did for P11 port, pins 1-3, 2-4, 5-7 & 6-8. This assumes for now we will use the RS232 socket J1.
For P24 jumper the bottom 3 pairs of jumpers, RHS. The is no connection to the P25 row of pins in our default configuration.

Boot up the V2 PDP11 CPU board.
Go to the "W" menu and use the 'D' option to send the '3' character to the TTY terminal 60 times via the Console/ODT UART U10.
A line of '3's should appear on your TTY terminal. The Board Select LED (D8) should briefly flash. If you do not see this go to the Monitor 'O' option and use the '3' menu option to send a byte to port FF76. Continuous '3's will be sent. If you do not see this on your TTY terminal back track and locate the problem. Do not go further unless you get this to work.

Next from the 'W' command use the 'E' and 'F' menu options to check the U10 UART's ability to send and receive characters using its status bits.

Next we will concentrate on interrupts received by the CONSOLE/ODT UART (U10).
For the ODT RCV Interrupt jumper P2 1-2 (Interrupt Priority) and P10 1-2 (Interrupt CLR0*).
Make sure you have the 6 pin ribbon cable connection between the PDP11 CPU board and this board connected.
Next boot your system, bring up the PDP11 Monitor.
Go again to the "W" menu and use the 'I' option to receive characters from your TTY terminal via the Console/ODT UART (U10).
You should see a display like this on your S100 bus console screen like this:-

Next lets activate the ODT XMT Interrupt. Jumper P2 5-6 and P10 5-6 and add Jumper K1 2-3.
Next boot your system, bring up the PDP11 Monitor.
Go again to the "W" menu and use the 'J' option to transmit characters from your TTY terminal via the Console/ODT UART (U10).
You should see a display like this on your S100 bus console screen like this:-

At this stage you have completed the construction of this board.

The UART Brake Signal.
The RS232 "Brake Signal" is not a character. It is a signal that can be sent using the TX line of the device sending the break. When a serial port is idle and no data is being sent the TX line is in a logical 1 state. While data is being send the TX line rapidly transitions between logical 0 and logical 1. Each frame of data takes a certain period of time to send, depending on the bit rate of the connection. This is called the "frame time" or "word time". A break occurs when the TX line is held to a logical 0 for longer than one frame time. It is seldom used today for serial transmissions but was used by Digital in their early PDP11 hardware. In fact its essential for example to load Tu58 tape drive data. On the Digital DL11 board setting bit 0 to 1 of the UART transmit status register forces a break signal on the RS232 line. The following code in the CPLD sets the TU58_BREAK_BIT pin (pin 76).

Pinnode = reg0;

reg0.d = S100_DO0;                      /* Bit 0 from a read of the TU58_XMT_STATUS_WRITE port */
reg0.ck = TU58_XMT_STATUS_WRITE;
reg0.ar = !bRESET;
!TU58_BREAK_BIT = reg0;                 /* Activate Break Bit on Port FF44 Bit 0*/

This is and'ed with the UART data out signal (U9B see the above first schematic on this page). In this way software can insert a Break signal (of any length ) into the UART data stream.

The PDP-11 Support Board Jumper Table
There are a fair number of jumpers on this CPU board and they need to be set carefully. Here is a typical jumper setup:-

Jumper	Function
P12	3-4, 5-6, 7-8. UART configuration
P11 & P16	1-2, 5-7, 2-4, 6-8. Serial input from DB9 Socket
K3, K4	Both 2-3. Utilize Printer Busy* & Ack* Status flags
P3, P22	7-8 (9600 Baud)
P2	1-2, 3-4, 5-6, 7-8, 15-16 (Interrupt Priority)
P10	1-2, 3-4, 5-6, 7-8, 15-16. (Interrupt Clear)
P9	1-2 (VI0*)
K2	2-3
P27	3-4 (Invert ACK*)
P20	1-2
K5	1-2
P4	1-2, 3-4
P19	1-2 (Assuming we are utilizing TMA0* to activate the PDP11 CPU Board).

PDP-11 S100 Board Parts
Most of the components are common. I usually get them from obtained from Anchor Electronics and Jameco.

PDP-11 CPU Board Bugs & Notes.
Please note there is a very important jumper on the V2 PDP11 CPU board that defines where the ODT UART status ports will be read from, it is the K14 jumper.   If it is set 2-3 then the CPU board expects all the required ODT UART status information to reside on the CPU board, furthermore it assumes this Support board is not in the S100 bus. If it is set 1-2, then the PDP11 monitor software and both boards hardware assume that the UART status bits will be processed on this Support board. It is essential you always have this K14 jumper positioned correctly. The V2 PDP11 CPU board will "hang" if this jumper is not set correctly and you set the K10 configuration switch to ODT console output mode.

I would like to acknowledge here Peter Schranz in Switzerland for the many times he has help me design this PDP-11 Support board. Without his tremendous experience of PDP11 hardware this board would not be possible for me. Peter is also setting up his own homebrew PDP-11 system, you can read all about it here.

Realizing that a number of people might want to utilize a board like this together with a group of people on the Google Groups S100Computers Forum, "group purchases" are made from time to time. Please see here for more information.

Finally please note, currently (March 2018),   the PDP-11 monitor is being actively updated. Please go to the PDP-11 Software page for the most current update.

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