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A PDP-11 Monitor
This monitor is for the S100 bus PDP-11 CPU board described here.   Unlike the Intel family of CPU's,  the PDP-11 starts up using a "Power On Circuit"  that either directs the CPU to its own internal (simple) monitor or to and external ROM.  This is all described in some detail here.

Here is how the monitor signs on when the CPU gets control of the S100 bus with the Z80 Monitor "O" command.
  
  Menu7
       
Please note this monitor is currently under active development (July 2017).  There are sections that call upon the "PDP-11 Support" board.  This board is still in the prototype stage and not available yet.  Please return here from time to time for updated versions.

Here is a list of the main functions within the PDP-11 monitor I have written so far:-

Setup all equates for ports and memory locations etc.
From the A-Z command jump table go to:-

Display memory map for 0 to FFFFH
XModem -- File downloads
Display RAM
Echo a keyboard character on console
Fill RAM with a HEX value (Bytes)
GoTo a RAM location
Fill RAM with a HEX value (Words)
Display the bit pattern of the IOBYTE port
Display menu on console
Rapid port ASCII output test to console
Move and verify memory
Query and set ports with Bytes or Words
Setup Interrupt vector table in RAM and activate all interrupts
Substitute values in RAM (Bytes)
Display ASCII in RAM
Test Speech output routine
Verify two RAM areas are the same
Tu58 Tape Drive Sub-Menu
Test Event timer
Turn off Interrupts
Switch back to Z80 CPU

Support routines

Table of pointers to routines within the monitor
Data area

Also please note there are various equates at the start of the monitor code that you need to adjust depending on your need (S100_ONLY, for example).
 
V2 PDP11 Monitor.
The V1.5 monitor almost completely fills the C000H to DFFFH available space on both the "V1" and V2 PDP11 CPU Boards.  On the V2 CPU board if we jumper K12  to 2-3 we can utilize pin 2 of the 28C64 EEPROMs to select the upper or lower "half" of the EEPROM as defined by its A12 address line.  Code in the U25 CPLD allows us to make this selection by inputting from the S100 bus ports 00E4H or 00E5H.  While this complicates the Monitor code it allows one to almost double the amount of code you can get into a 4K address space. All versions of the PDP11 Monitor from V2.0 onwards have this capability/code.  The most current version can be download from below.   Programming these two EEPROMS is a bit tricky however.  First here is a diagram of the layout:
  
  ROM Layout
 
The actual PDP monitor assembly language code is split into two completely separate files, PDP_MON_LOW_PAGE.MAC  and PDP_MON_HIGH_PAGE.MAC.  It is very important to understand that the code in either file knows nothing about the code in the other.  The vast majority of the monitor code (currently) resides in the PDP_MON_LOW.MAC file. In fact you can use this code/file alone to run the monitor just as you did for the earlier "single page" monitor e.g. the V1.5 monitor.  It will for example run fine in the original V1.1 PDP11 CPU board.  Currently two menu options, The "C" (XModem) and "O" (IO Ports) commands reside in the High Page for the V2 and later versions.  Any further new code will probably also reside there. 

How do we switch the Address Line LA13 on the ROM without blowing the running CPU out of the water?   We do this by having a small "Switch Address Line" routine in exactly the same location in both the LOW and HIGH ROM code sections.  In both files (and so pages of the ROM) the beginning code is:-

LOW PAGE ROM:-
Start: MOV #CPU_STACK,SP            ; LOW ROM & HIGH PAGEs: Setup stack at BF00H (Below ROM ORG at C000H)
       MOV #&00E0,@#PSW             ; Block ALL Interrupts (Clear bits 7-5)
       JMP SKIP                     ; Skip to the hardware initialization/running
Align
ACTIVATE_HIGH_PAGE:                 ; SWITCH TO HIGH PAGE ROM
      
MOVB @#ROM_HIGH_PORT,R1      ; Switch the LA13 Address line input to the ROMs HIGH. MUST be to an even byte
       JMP NoHighPageError          ; Will arrive here only IF no address line LA13 switch. Must be inactive (Check JP K12)
Align
ACTIVATE_LOW_PAGE:                  ; RETURN BACK TO LOW PAGE ROM
      
NOP
       NOP                         
       JMP Loop1
                   ; <---- Switching back to LOW page will arrive here

SKIP:
______________________________________________________________________________________________________________

HIGH PAGE ROM:-
Start: MOV #CPU_STACK,SP            ; LOW ROM & HIGH PAGEs: Setup stack at BF00H (Below ROM ORG at C000H)
       MOV #&00E0,@#PSW             ; Block ALL Interrupts (Clear bits 7-5)
       JMP NoLowPageError

Align
ACTIVATE_HIGH_PAGE:                  ; <---- ARRIVE HERE FROM LOW PAGE
     
 NOP
       NOP
       JMP HIGH_Loop

Align
ACTIVATE_LOW_PAGE:                   ; <----- JUMP BACK TO LOW PAGE
      
MOVB @#ROM_LOW_PORT,R1        ; Switch the LA13 Address line input to the ROMs LOW. MUST be to an even byte
       JMP NoLowPageError            ; Will arrive here only IF no address line LA13 switch. Must be inactive (Check JP K12)

NoLowPageError:

The trick is that when we input (anything) from the port ROM_HIGH_PORT the code in the U25 CPLD recognizes this event and switches the address line LA13 from LOW to HIGH going to both EEPROMS.   The yellow text code above moves (unknown to the CPU) from the lower to the upper ROM page.  This common code is the link between both pages.  We load a menu option number into the R3 register, jump to the "Switching Routine", it is picked up in the HIGH page and processed in the normal way depending on the R3 menu number passed to it. 

When done, we jump to the ACTIVETE_LOW PAGE which lowers the LA13 line  and again, unknown to the CPU it  ends up in the LOW PAGE.  This code is in purple above.
It takes a little time to really understand this process.  Remember the CPU does not know anything about this process. After the port input is done the CPU does whatever the next opcode in that ROM (page) requires.    

This facility allows us plenty of future space to write quite elaborate functions in the 4K (now 8K) ROM space between C000H and DFFFH on the V2 CPU board.

There is however one catch, programming the ROMs is quite tricky.  You have to place the 4 segments of code exactly as shown in the above diagram.   It would be easier if our assembler generate .HEX code but it only generates .bin files.   You are already familiar by now I assume of burning the .bin file EVEN and ODD bytes into two ROMS.   The added twist here is we need to place two files in the EVEN bytes ROM and two files in the ODD bytes ROM.  You have to be careful when you load up the second file you don't overwrite the first file.

Different PROM Burners probably have different ways of doing this. Here is the process for a  Wellon VP-290 (or VP299) with 28C64's EEPROMS :-

Assemble and make two .bin files, PLP_MON_LOW_PAGE.bin  and PDP_MON_HIGH_PAGE.bin.  
Be sure you configure the equates at the start of both files correctly before assembly.  In particular make sure you have:

ROM:   equ   TRUE


For the EVEN bytes ROM:-

Load the Wellon programmer program.
From the Edit menu Fill the buffer with 00's and close it.
Load the file PDP_MON_LOW_PAGE.bin with the following settings:

For File Mode use "Even" and Clear Buffer Options = Disable
Leave the "File Address(Hex) as 0000 and the "To Buffer Address (HEX) as 0000H)
For "Auto Format Detect" use bin
Leave the File size (for a 28C64) to 2000H

Load the file PDP_MON_HIGH_PAGE.bin with the following settings:

For File Mode use "Even" and Clear Buffer Options = Disable
Set the "To Buffer Address (HEX) as 1000  and the "File Address(Hex) as 0000)
For "Auto Format Detect" use bin
Set the File size (for a 28C64) to 1000H

Program ("Burn" ) the above ROM code.
When done, read the data back with the Read button.  Then open the Edit buffer and scroll down the 100H sections.  You should see the following:-
   
  ROM Burns1

Repeat for the ODD bytes ROM:-
From the Edit menu Fill the buffer with 00's and close it.
Load the file PDP_MON_LOW_PAGE.bin with the following settings:

For File Mode use "Odd" and Clear Buffer Options = Disable
Leave the "File Address(Hex) as 0000 and the "To Buffer Address (HEX) as 0000H)
For "Auto Format Detect" use bin
Set the File size (for a 28C64) to 2000H

Load the file PDP_MON_HIGH_PAGE.bin with the following settings:

For File Mode use "Odd" and Clear Buffer Options = Disable
Set the "To Buffer Address (HEX) as 1000  and the "File Address(Hex) as 0000)
For "Auto Format Detect" use bin
Set the File size (for a 28C64) to 1000H

Program ("Burn" ) the above ROM code.
When done, read the data back with the Read button.  Then open the Edit buffer and scroll down the 100H sections.  You should see the following:-
 
  ROM Burns2
  
With this dual page feature you have an extended list of Monitor options. The HIGH PAGE options currently are the "C" and "O" commands.  They have square brackets around them in the menu, but otherwise behave exactly like the other menu items.   Obviously if you are using the V1.1 Board or only burn in the LOW ROM PAGE they will not be available.  The monitor code will detect this and warn you.

Here is what the monitor signon looks like for a few commands.
 
  V2 main menu

  A Command   W Command
       
  O Command   C Command
   
As you can see programming both EEROMS is quite tricky. Some ROM programmers may not in fact let you do a reburn as described above.  When you are first building your board (or for the V1 board) just use the PDP_ROM_LOW_PAGE file and use do a simple "normal" Odd/Even ROM burn.  Remember you do not need the HIGH page mode to boot up the monitor. 

Please remember this PDP11 Monitor contains a few critical equates at he start of both the HIGH and LOW Page listings. Take care to set then exactly to suite your needs.

ROMS: equ TRUE                      ; <<<<< Set to FALSE for test program running at 1000H in RAM (10000 Octal) >>>>>

DETAILED_INTS: equ TRUE             ; Set to TRUE for detailed UART Interrupt data display. (Note characters must be entered slowly)
ST8C4: equ FALSE                    ; FALSE if LP11 Printer output. TRUE (only) if output is to the S100_Parallel_IO Board.
S100_ONLY: equ FALSE                ; <----- If TRUE will skip checking to see if console IO should go to the UART
                                    ; will always sent to Console IO board (Switch K10 is ignored on the CPU board).
ODT_ONLY: equ FALSE                 ; <----- If TRUE will skip checking and always send console IO to the ODT UART


Please see here for additional PDP11 Software.

The links below will contain the most recent versions of the above software.
Note, it may change over time and may not correlate exactly with the text in the article above.

DC-11 User Guide                                                                     ( 2/13/2017)
PDP-11 Programmers Card                                                   ( 4/5/2017)
AsmPDP Assembler (Zip File)                           ( 4/5/2017)    
(From http://mdfs.net/Software/PDP11/Assembler) 

PDP.MONITOR (V1.5) .MAC file)                                       (12/5/2017)
PDP.MONITOR (V1.5)  (Zip File)                        (12/5/2017)

PDP_MON_LOW_PAGE (V2.3) (.MAC File)            (12/18/2017)
PDP_MON_HIGH_PAGE (V2.3) (.MAC File)           (12/18/2017)
PDP.MONITOR (V2.3)  (Zip Files)                        (12/18/2017)

This page was last modified on 03/05/2018