The "MEMORY BANK" was a 64K dynamic RAM memory board. It could be used as a
standard 8-bit wide memory board, or as a 16-bit by 32K memory board, either
by a parallel transfer of 16 bits through a bidirectional gated data bus, or
by a sequential transfer of a high byte and a low byte. In this, it follows
the conventions established by IEEE Standard 696.
The board could be selected by port addressing per Northstar/Cromemco/Alpha
Micro/SD Systems convention, or by using the full 24-bit extended address
bus proposed by the IEEE standard. It was garunteed to be compatible with
the following CPU products: SD Systems
SBC-200, Jades own
"Big Z" CPU,
Ithaca Intersystems Z80-II board, the
Solid State Music CB2
Z80 board, the
Cromemco ZPU,
TDL's ZPU and the
Northstar ZPB-A.
Although the board was designed specifically for use with Z80 and Z8000-type
systems, it operated successfully with other CPU types that met the timing
specifications of the S-100 bus and were capable of providing a
memory-request signal similar to that of the Z80. Its timing was
designed such that it may be used up to 6 MHz with proper RAM chip
selections and without board modification.
The board also provided an on-board M1 wait state generator and a unique RAM
pre-charge extender which functions without adding wait states to the memory
cycle, yet allows slower RAM chips to be used with 4 MHz and 6 MHz CPU
chips.
The board performed its refresh cycles transparently to all CPUs and was
capable of being used with DMA devices and disk controllers which utilize
extended wait states.
Any 16K bank could be disabled by switch selection. In addition, special
circuitry existed on the board that can deselect the top 4K or 8K of memory
space, allowing its use with CPU types that have on-board EPROM monitor
programs or boot programs without provision for disabling RAM memory when it
is in conflict with the EPROM location.
The manual for this board can be obtained
here.
