S100 Computers - OPL3 Board

The OPL3 Game & Serial S100 Bus Board.

Introduction
David Fry in the UK has designed an S100 board that is very useful for incorporating game controls on the S100 bus as well as some other extra capabilities. What I have here is essentially Dave's work. I am presenting it here with his permission. If you have specific questions or comments about the board and its related software, please contact him directly. Dave is a regular contributor to the Google Groups S100Computers forum.

OVERVIEW
The full schematic diagram of the S100 OPL3/Game/Serial board is actually quite a ‘busy’ diagram by virtue of the multi-function nature of the board and all its supporting circuitry. It is the intention that this document will help to clarify the operation of the unique functional areas of this board so that the end user may be confident to troubleshoot any issues that may arise whilst building and configuring the board.More familiar circuitry such as bus drivers, signal buffers and power supplies will not be discussed as it is assumed to be understood from familiarity with other S100 boards.

I/O Port Addressing

The I/O port decoding circuitry is comprised of two 22V10 GALS (U1 & U2) and six 74LS682N 8 bit magnitude comparators. This combination of IC’s provides independent 8 bit and 16 bit port addresses across all three board functions giving better control over I/O port resource allocation.

The 74LS682N 8 bit magnitude comparator circuit should be familiar territory for most of us, essentially this IC compares two binary 8 bit words fed into two 8 bit ports, if the data on both 8 bit ports match then the output pin 19 will go active LOW to signify a match, in all other cases pin 19 will be high.

We can see from the diagram extract below (fig 1) that a subset of the buffered CPU address lines are connected to one 8 bit port (P0 -> P7) and the second 8 bit port is connected to a 8 way DIL switch permitting the user to specify the I/O address to match. The 74LS682 that decodes the 16 bit address space has an extra 3 pin header that permits the selection of one of two

Pre programmed upper 8 bit addresses (bA8 -> bA15) 02xxH or 03xxH this allows standard IBM PC I/O port addresses to be configured.

Now as it stands the magnitude comparator outputs will pulse low every time the connected address lines match the DIL switch settings regardless of whether the CPU is generating a memory access or I/O port access, therefore further qualification of the pin 19 outputs are required using the S100 bus control signals.

It should also be noted as you review the 3 groupings of 74LS682’s that some port inputs are not used and connected to GND, in these cases the corresponding DIL switch will always be in the ‘ON’ position for correct operation. These same switches also provide a convenient way to disable a particular board function (OPL3/Game/Serial) if required by placing the switch in an open position creating a situation where there can never be a comparator match.

Turning our attention to the two GALS U2 and U1 (fig 2) I will try to explain how these two devices work together with the 74LS682’s to provide fully decoded I/O addressing.

Starting with the first equation in U2

P_03xxH = /A15 * /A14 * /A13 * /A12 * /A11 * /A10 * A9 * A8

P_02xxH = /A15 * /A14 * /A13 * /A12 * /A11 * /A10 * A9 * /A8

The above two equations produce two outputs on pins 18 & 19 corresponding to 03xxH and 02xxH, these outputs are then wired to the 3 pin headers K2,K3,K4 (shown in fig1) satisfying the upper byte requirement of a 16 bit address space.

The magnitude comparator outputs from all six 74LS682’s are then passed into pins 6,7,8,9,10 & 11 of GAL U2 as unqualified decoded 8 and 16 bit addresses for the 3 board functions (OPL3/Game/Serial).

Remember, at this stage the pin 19 outputs will go active low on any address line match whether it is an I/O or memory cycle.

The next three equations in GAL U2 complete the decoding of the Chip Select lines by ‘ANDing’ the unqualified decoded 8 & 16 bit address’s with IO_REQUEST and 16BIT, these inputs are generated by GAL U1 and enter GAL U2 as inputs on pins 13 & 14.

Note how each Chip Select equation has two expressions, one line for 16 bit and the other line for 8bit decoding. The active line is determined by the logical state of the 16BIT status input.

/GAME_CS = /GAME_16CS * 16BIT * IO_REQUEST

+ /GAME_8CS * /16BIT * IO_REQUEST

/UART_CS = /UART_16CS * 16BIT * IO_REQUEST

+ /UART_8CS * /16BIT * IO_REQUEST

/OPL3_CS = /OPL3_16CS * 16BIT * IO_REQUEST

+ /OPL3_8CS * /16BIT * IO_REQUEST

The fully I/O decoded Chip Select lines are finally output on GAL U2 pins 15, 16 & 17

Having generated the Chip Select signals in GAL U2 we now turn to GAL U1 to examine its role in the overall design. The outputs of the first two equations are mentioned in the section above.

IO_REQUEST = sINP + sOUT

The first equation generates the I/O request signal using the S100 bus signals sINP and sOUT to identify a I/O port bus cycle, this signal is output on pin 21 passed to GAL U2 pin 13

/16BIT = TMA0 * TMA1 * TMA2 * TMA3

The 16 bit port address status signal is generated by ‘NANDing’ all 4 TMA lines together, if any one of the TMA lines go LOW then the output will go HIGH indicating a 16 bit CPU board is active.

So referring to (fig 2) we add a jumper to each TMA location that would be pulled low by a 16bit CPU board thus enabling GAL U1 to distinguish between 8 bit and 16 bit port address requirement.

The 16BIT signal is output on pin 20 and passed to GAL U2 pin 14.

/RD = pDBIN * sINP

/WR = /pWR * sOUT

The Read and Write control signals are again generated from S100 bus signals and are used to control/indicate data direction. Used by the on board devices and the data bus buffers.

PORT_SEL = OPL3_CS * UART_CS * GAME_CS

Finally, the PORT_SEL status signal is generated from the fully decoded Chip Select signals. If any one of the three Chip Select signal goes active LOW then the PORT_SEL signal will also go low allowing data to pass over the data bus buffers.

The PORT_SEL signal is output on pin 16 and connects to U8 pin 2 & 4

Game Port Circuit

Moving on to the first of the three board functions the core of the game or joystick port circuit is a direct implementation of the circuit published in the IBM technical reference manual for the PC XT.

This circuit changed very little over the early development of the PC with the NE558 clearly seen on many PC ISA bus soundcards of the era before this circuit functionality was moved inside of sound card ASICs.

Circuit operation is actually very simple, the NE558 contains 4 timers whose output pulse width is determined by the time constant of a capacitor (C11, C12, C18 & C21) and variable resistor (Joystick) in series with a fixed resistor (R3, R4, R5 & R6). The fixed resistors set the minimum pulse width of the timer to ensure that the pulse is measureable under software.

The output pulse (high) begins with the triggering of the timer inputs on pins 3,6,11 & 14 by performing a write operation to the game I/O port (the actual value written is irrelevant as it is not used). Following this write operation the Game I/O port is now read by software polling method to determine the width or length of time each channel takes to return to zero. The values obtained are used to determine the X-Y axis position of the two joystick units. Provision has also been made to poll the status of two buttons per joystick using the spare 4 bits available on the I/O port.

So looking at (fig3) and working from the top, P2 is the 16 way 0.1” header which is wired to match the joystick plug standard pin out (so pin 1 to pin 1, 2 to 2 etc...) allowing IDC connectors to be used to make a patch cable. The +5v supply to the joystick is protected by a 100 ohm resistor R34 to protect the fine PCB traces against burn out in the event of an accidental short or faulty joystick controller. Resistors R22 to R25 are pull up resistors for the joystick buttons which are in turn wired to D4 to D7 through U13. The NE558 has open collector outputs so RR3 serves to pull these to the 5v rail to meet TTL levels.

Finally, U8C and U8D provide the necessary read/write steering to trigger the NE558 timers on an I/O write cycle and enable the octal buffer (74LS244) on a read I/O cycle to enable the joystick data to be read.

Serial Port Circuit

The simplicity of the serial port circuit conceals the complexity that lies within the PC16550 chip itself, the 3 address lines (A0 to A2) on pins 26, 27 & 28 evidence that the PC16550 uses eight consecutive I/O ports to address the internal configuration registers. Further study of the PC16550 datasheet will be required for those who wish to develop code for this chip.

For a starting point I have included some Z80 code (separate file) for an X-modem routine, the code was brought together from various sources, credits given in the listing header.

The MAX239 (U21) provides TTL to RS232 level shifting duties for the PC16550, the full complement of serial port signals are made available on output header P9 (via patching headers P8 & P10) wired according to the standard male DE-9 serial plug specification.

It goes without saying that this configuration was chosen to provide an extra PC compliant serial port under MS-DOS on the S100 bus.

OPL3 Adlib Sound (Digital)

The digital section of the OPL3 sound circuit is stock datasheet implementation.

Examining an ISA sound card I had to hand and comparing to the YMF262/YAC512 datasheets this would seem to be standard practice.

Points of note:-

The Yamaha YMF262 supports up to 4 channel output (Channels A,B,C & D) requiring two YAC512 stereo DAC chips, in our application (PC Adlib sound) we are only interested in channels A + B so the four YMF262 DAC digital interface lines we are interested in are pin 23 (data clock), pin 21 (Channel AB data stream), and pins 19 & 20 which identify the L & R components of the data stream as it is clocked into the corresponding L or R DAC registers.

The YAC512 utilizes two external op-amps for buffering duties, the first one U9B buffers the internal 2.5v voltage reference which drives the internal D-A level shifter. The second op-amp U9A buffers the D-A level shifter output (which handles analog sample data for both L + R channels) and passes back to the internal L + R sample & hold switches. Resistor R7 sets a time constant with the sample & hold capacitors to help with removal of high frequency switching transients prior to further filtering.

OPL3 Adlib Sound (Analog)

The analog section of the OPL3 sound circuit is below

It is divided into 3 distinct sections, sample & hold buffer, low pass filter, and output amplifier.

Sample and Hold Buffer

Referring back to the previous section we mentioned that the L + R outputs of the DAC (YAC512M) are sample and hold switches, this means that each output channel presents the analog sample voltage for slightly less than 50% of the time. Use of a holding capacitor followed by a buffer op-amp allows the circuit to maintain or ‘hold’ this sample voltage until the next analog sample voltage is presented. In order to prevent this voltage leaking away between samples a low input current FET audio op-amp is used to buffer the signal and drive the low pass filter.

During my initial research for this card I tried to determine which DAC channel (A or B) corresponded to left or right, it turns out that some sound card manufacturers wire it one way and some the other. Clearly one way is correct and the other wrong so I added in a patch block to allow the end user to determine for their self.

Low Pass Filter

The low pass filter circuit serves to remove any sampling noise products and to this end has a 18db/octave slope with cut off frequency around 15khz (FM radio quality), this combined with the YMF262 sample rate of 49.7khz places the sampling noise components some 60dB below the audio signal.

The 18dB/octave filter slope is formed first by a 6dB/octave passive filter (R35 + C68) and this is followed by a 12dB/octave active filter centered around op-amp U15A which is configured for a gain of 2.2 (6.8dB).

One of the obstacles that need to be dealt with is the removal of the DC component in the audio signal as the YAC512 DAC biases the output audio signal on a DC voltage of ½ VCC (center point). Since we also now have some gain in the low pass filter if we did nothing then the audio signal output of the low pass filter would now be sat on a DC level of 5.5v. The original OPL2 Adlib card used a bit of a kludge to deal with this situation using a transistor to remove the charge across a DC blocking capacitor. I have adopted a different approach by incorporating a DC servo (U15B) in the low pass filter feedback loop and this effectively removes the DC component of the filtered audio signal by raising the DC input voltage on the inverting input of U15A. In essence the two op-amps work in tandem each having its feedback loop closed by the other device but in different frequency ranges to achieve the desired result.

Output Amplifier

Output amplifier duties are handled by a NE5532 dual op-amp IC, this IC is well known in the audio community for its good sound, good output drive capability, and low price. The circuit is a fairly simple headphone amplifier with a fixed gain of 3 (9.5dB) which at full volume allows the output voltage to swing to approx. 7v p-p, enough to drive a pair of high impedance headphones or at slightly lower listening level a pair of 32 ohm in ear phones. Resistors R48 + R49 serve to prevent output current clipping (protecting the op-amp) when driving low impedance earphones.

The board also has a fixed line level output connector for audio connection to a pair of active speakers.

Every effort has been made to preserve audio quality in the analog circuitry through the use of a split rail power supply, polyester film capacitors and Nichicon FG audio grade electrolytic capacitors. I would recommend using the parts suggested in the BOM as the cost difference is negligible.

The above is a brief schematic overview in explaining the fundamental operation of the 3 main circuit functions, In the full schematic (see below) there are various other circuit elements. Many of these are common to the other S100Computer.com boards and should be familiar to most builders.

If you have any further queries regarding a certain aspect of circuit operation then please post a question to the S100Computers Google Groups forum and David will try his best to answer.

GAL Code

What follows below is the full PALASM design descriptions for the two GALs (U1 & U2) used in this project. See here for more information on GALs

;---------------------------------- PIN Declarations --------------- PIN 1 NC ; Not Currently Used PIN 2 A11 ; (H) INPUT PIN 3 A10 ; (H) INPUT PIN 4 A9 ; (H) INPUT PIN 5 A8 ; (H) INPUT PIN 6 GAME_16CS ; (L) INPUT PIN 7 GAME_8CS ; (L) INPUT PIN 8 UART_16CS ; (L) INPUT PIN 9 UART_8CS ; (L) INPUT PIN 10 OPL3_16CS ; (L) INPUT PIN 11 OPL3_8CS ; (L) INPUT PIN 13 IO_REQUEST ; (H) INPUT PIN 14 16BIT ; (H) INPUT PIN 15 OPL3_CS ; (L) OUTPUT PIN 16 UART_CS ; (L) OUTPUT PIN 17 GAME_CS ; (L) OUTPUT PIN 18 P_03xxH ; (H) OUTPUT PIN 19 P_02xxH ; (H) OUTPUT PIN 20 A12 ; (H) INPUT PIN 21 A13 ; (H) INPUT PIN 22 A14 ; (H) INPUT PIN 23 A15 ; (H) INPUT

EQUATIONS P_03xxH = /A15 * /A14 * /A13 * /A12 * /A11 * /A10 * A9 * A8 P_02xxH = /A15 * /A14 * /A13 * /A12 * /A11 * /A10 * A9 * /A8 /GAME_CS = /GAME_16CS * 16BIT * IO_REQUEST + /GAME_8CS * /16BIT * IO_REQUEST /UART_CS = /UART_16CS * 16BIT * IO_REQUEST + /UART_8CS * /16BIT * IO_REQUEST /OPL3_CS = /OPL3_16CS * 16BIT * IO_REQUEST + /OPL3_8CS * /16BIT * IO_REQUEST

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