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Re: [N8VEM-S100:990] 512MB DRAM / S-100 Card
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Yes, I agree, let's chew on that for a little bit and see if we can't
come up with something.
I was actually thinking along those same lines myself as well the last
couple of days, but wanted to finish fleshing out the other option
first so we have at least one realizable plan under our belt.
I don't know with any degree of certainty what it would take to
interface with modern DDR memory. I'd have to catch up on the intimate
details of modern DDR memory controllers.
What I do know is that timing relationships are more complex for sure
because you have the data coming in (or out) on both the rising and
falling clock edges...etc...
It seems that most of the DDR and DDR2 controllers that you can
purchase are implemented in a FPGA and there are a number of them
available apparently, I know little about them (i.e. to they do
voltage level translation, and so on?)..
If I'm not mistaken DDR I/O operates in the ~2.5V range and DDR2 in
the ~1.5V range (I don't think we should even look at DDR3). So
there's that issue to contend with as well.
Also data is transferred 64 bits at a time. So how to contend with
mapping a 64 bit bus to a 32 bit bus.
I'm sure I'm just scratching the surface of the issues related to
interfacing with these bad boys.
In any case, to answer your previous question, yes, I am pretty much
up to my neck, but I would be willing to commit to doing some further
research and a first pass of the ram board schematic, beyond that,
I'll do what I can.
On 07/17/2012 02:03 PM, John Monahan wrote:
> Mike thinking some more, before we go for this route are you sure
> there is not a way to refresh one modern day PC style Gigabyte
> DDRAM type SIMM with a crude binary counter slamming wait states
> back to the CPU in the process. The clock speeds we would be using
> are way lower that what these DRAMS are expecting. It seem such a
> shame to have to be using 4X132 pin chips and 8 DRAM SIMMS with
> what is available today.
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