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Re: [N8VEM-S100:967] V96BMC-33LP - More documents

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Actually the basic access timing diagram in the one document shows
~BLAST falling at the rising edge of the first PCLK and the other
shows at the first falling edge, so maybe PCLK is not the right
reference, perhaps it's relative to ~ADS?

In any case, it looks like the idea is that you assert ~BLAST shortly
after the beginning of the transaction cycle, and that indicates that
it is basic access I think.

- --Mike

On 07/16/2012 01:33 AM, mike wrote:
> My understanding is that the device is capable of doing burst mode
> or basic access mode.
> If you look at the timing diagrams that show basic timing vs burst 
> mode timing it looks like to do basic timing you would have to come
> up with something that would simulate ~BLAST on the first falling
> PCLK at the start of a read or write since I don't think the 386
> has a BLAST signal (i.e. does not have a burst mode).
> Don't take that to the bank, but that's my take on it so far.
> --Mike
> On 07/16/2012 01:11 AM, John Monahan wrote:
>> It looks like it only does "Burst mode refresh".  Can this
>> refresh mode be done with the 80386.   Are special DRAM chips
>> required. John
>> John Monahan Ph.D e-mail: mon...@vitasoft.org Text: 
>> mon...@txt.att.net
>> -----Original Message----- From: n8vem...@googlegroups.com 
>> [mailto:n8vem...@googlegroups.com] On Behalf Of mike Sent: 
>> Sunday, July 15, 2012 8:47 PM Cc: n8vem...@googlegroups.com 
>> Subject: [N8VEM-S100:962] V96BMC-33LP - More documents
>> More documents on the V96BMC chip.
>> There is one document that covers programming the plain V96BMC 
>> (not Rev-D) so only appear to be capable of driving 256MB DRAMs
>> but should be pretty similar. I'll continue to see if I can find
>> the programming data for Rev-D.
>> --Mike

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