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Being IEE compatible of course it could use 16 or 24bit addressing. It could be stocked with 256K X1 or 64K X1 RAM chips. There were 9 chips per block. This allow for a parity bit per byte. A parity error could be returned on the S100 lines NMI*, the 8 VI'* lines or ERROR*. There were a number of I/O port options to query the nature of the error and reset it.
As with the 256K board, memory was organized in 2 blocks, each occupying 1/2 of the address space. There was an S-100 phantom disable which could be disabled by a switch on board. There was a switch also to select A0 or A0* as the most significant byte on the bus. Access time was very fast, 175 nsec from SMEMR or pSYNC high. This allowed a Z80 to get to 6MHz or the 8086 and 68K familys to get to 8MHz.
The manual for this board can be obtained here.
This page was last modified on 06/26/2015