Hi! I finally got a chance to work on the S-100 Utility board again. I added the RP5C01 Real Time Clock circuit so I think our MSX2 compatibility should be complete now. Please review this schematic and PCB layout and send me any changes and/or corrections.
This would make a good board for those who want to boot strap a bare CPU board only S-100 system. Thanks and have a nice day! From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Andrew Lynch Thanks John! No problem! I am holding off on making S-100 Utility prototypes until the design is vetted properly. I don’t want to waste Leon’s or your time with a half-baked prototype board for build and test. Especially if it is easy stuff I overlooked. This is purely notional discussion for now. No prototype PCBs until it is ready! From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of John Monahan Andrew could you give me a couple of days, I would like to see/be sure we could seat this board in an IEEE-696 bus and have the option of it being transparently being there unless “activated” but once that is done it would have to phantom out any conflicts with other boards. John From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Andrew Lynch Hi, Thanks Antony! Great observation! This is precisely why I am asking for some peer review of the S-100 Utility board design. There are some truly strange things happening and they all seem centered around the 8255 PPI which drives the memory banking circuitry. I’ve not seen anything like it but it surely is a neat design. Yes good point on the U21B.5 connection. I’ve been scratching my head over it. I think in the schematic it refers to /Y5 or Y5* which is an output of the IO decoder 74LS138 pin 10. It connects to /CS which is in turn connected to the 8255 PPI chip select. Why they called it /Y5 instead of /CS makes no sense to me. It occurs nowhere else in the schematic AFAIK. I think what the two 74LS00s are doing is forming a flip-flop (S-R?) in front of the memory banking multiplexer. Once the 8255 is accessed, it toggles the multiplexer to get the next set of values. http://en.wikibooks.org/wiki/Digital_Circuits/Latches If you look at “MSX hardware notes part 2” document on page 7 it more clearly spells out the set input (S?) to the flip flop is intended to be the 8255 chip select line. Regarding the 74LS682s, we could simplify the IO decoding by using a hard wired logic. However I’d like to keep the board general in nature. Although I’d like it to be MSX hardware compatible I suspect many (most) builders could care less about MSX and will want to move the IO block around to suit their particular machines. The 74LS682’s keep the design “general” enough so that it can be customized without resorting to “cuts and jumpers”. Although all the N8VEM builders just *love* cuts and jumpers! As a consequence of the separation of the V9938 and AY-3-8910 into its own board (S-100 VDP) and the rest on the S-100 Utility board there is a bit of redundant IO decoding between the two boards. For a final design I will eliminate the V9938 and AY-3-8910 unique IO decoding (U34 & U35 gates) since they are handled on the S-100 VDP. It will save us a chip! Woo Hoo! Thank you very much for the analytical and critical review of the S-100 Utility board. Please continue and hopefully others will join in. The better we scrub the schematic and PCB layout now, the more successful the follow on builders in build and test will be. Fewer “cuts and jumpers” for everyone! Also there is less sending Leon and John on wild goose chases with my goofy prototype boards! Have a nice day! From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Ants Pants Had a look over the schematic CrossRef with the msx tech manual and looks ok, U21B.5 i have connected to the PPICS* signal though, question: do we need the "board select" switches/682's ? is the board in reality more likely to just have straight address decoding via U33 to the PPI, Printer, UART? and the addresses fed straight to the various ROM, RAM, and I/O ? the only brains of the operation is the PPI which selects which chip select lines to get enabled at which addresses of 16KB blocks? the VDP and Sound board however will need the address decoding as we dont want to route out U33 pin(s) 11 and 12 to the PSG and VDP respectively. [URL="" href="http://img855.imageshack.us/img855/5489/do2b.jpg%5b/IMG%5d%5b/URL">http://img855.imageshack.us/img855/5489/do2b.jpg[/IMG][/URL] looking forward to this board!!
Hi As you may already know, at the N8VEM project we are working on an S-100 VDP. This board has a V9939 video display processor and a AY-3-8910 sound generator which should allow us to have some MSX2 compatibility when combined with a backplane, S-100 Z80 CPU board, and a memory board. There are more IO and memory features necessary for full MSX2 compatibility required though. I am considering a designing a board to provide the balance of MSX2 functions so that the combination of an S-100 backplane, S-100 Z80 CPU, and S-100 VDP. I envision such a board to be composed of SRAM memory, a couple of 8255 PPIs, a card slot plus whatever extra IO and memory we need. If anyone has detailed MSX2 experience and would like to help out on designing an S-100 MSX2 compatibility board to complement the S-100 VDP please contact me. S-100 and MSX seem like a neat combination but no one has tried it AFAIK. Thanks and have a nice day! -- -- -- -- |
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