Hi, Thanks Antony! Great observation! This is precisely why I am asking for some peer review of the S-100 Utility board design. There are some truly strange things happening and they all seem centered around the 8255 PPI which drives the memory banking circuitry. I’ve not seen anything like it but it surely is a neat design.
Yes good point on the U21B.5 connection. I’ve been scratching my head over it. I think in the schematic it refers to /Y5 or Y5* which is an output of the IO decoder 74LS138 pin 10. It connects to /CS which is in turn connected to the 8255 PPI chip select. Why they called it /Y5 instead of /CS makes no sense to me. It occurs nowhere else in the schematic AFAIK. I think what the two 74LS00s are doing is forming a flip-flop (S-R?) in front of the memory banking multiplexer. Once the 8255 is accessed, it toggles the multiplexer to get the next set of values.
If you look at “MSX hardware notes part 2” document on page 7 it more clearly spells out the set input (S?) to the flip flop is intended to be the 8255 chip select line.
Regarding the 74LS682s, we could simplify the IO decoding by using a hard wired logic. However I’d like to keep the board general in nature. Although I’d like it to be MSX hardware compatible I suspect many (most) builders could care less about MSX and will want to move the IO block around to suit their particular machines. The 74LS682’s keep the design “general” enough so that it can be customized without resorting to “cuts and jumpers”. Although all the N8VEM builders just *love* cuts and jumpers!
As a consequence of the separation of the V9938 and AY-3-8910 into its own board (S-100 VDP) and the rest on the S-100 Utility board there is a bit of redundant IO decoding between the two boards. For a final design I will eliminate the V9938 and AY-3-8910 unique IO decoding (U34 & U35 gates) since they are handled on the S-100 VDP. It will save us a chip! Woo Hoo!
Thank you very much for the analytical and critical review of the S-100 Utility board. Please continue and hopefully others will join in. The better we scrub the schematic and PCB layout now, the more successful the follow on builders in build and test will be. Fewer “cuts and jumpers” for everyone! Also there is less sending Leon and John on wild goose chases with my goofy prototype boards!
Have a nice day!