Hi guys. Having just finished our 80286 S-100 master/slave S-100 board, see here:-
I am thinking how to do the 80386 S-100 board. In a sense it’s easier from a hardware perspective since the jump from 8086 to 80286 in more than 80286 to 80386. As we know the 80286 is really just a fast 8086 (and was used as such).
The 80386 really was a new breed and could run some decent software. That is why I would like to make a new S-100 board. Since the 80386 has a 16 bit access pin it’s easy to have it address the low RAM on the S-100 bus. It would behave like the 80286. However to take advantage of the 32 bit data bus and address lines I’m thinking of having a daughter board with an over the top connecting cable for all that extra RAM capacity.
The question is; should I use static RAM or DRAM. Static RAM is easy to interface, but even with SMT chips lower capacity. With DRAM SIMMS we could have a decent Linux going.
My question to this group is does anybody have a suggestion for a good refresh controller chip/circuit. It’s particularly tricky because sometimes the CPU will not have access to the bus and will be held in its reset state, (Another CPU is running the S-100 Bus). Alternatively anybody know about “Pseudo Static RAM” chips. Apparently these are self-contained with their own internal refresh. Don’t know how they are accessed.