RE: [N8VEM-S100:914] An 80386 S-100 Board.

Hi! Please take a look at this documentation for an S-100 80386DX board that’s capable of running a “sophisticated” operating system like Linux or NetBSD:

http://bitsavers.org/pdf/intel/_dataBooks/1987_80386_Hardware_Reference_Manual.pdf

I agree the “over the top” daughter board may be necessary for all the components. I suggest we place all the CPU and bus control logic on the main CPU board and use a pair of the newer 40 pin (80 wire) IDE connectors to export all the memory and its interface logic to another board.

In the Intel 80386 Hardware Reference Manual there are circuits for interfacing EPROM and DRAM chips. I recommend using the 72 pin DRAM SIMMs since they are “regular” DRAM chips packed on to mini circuit boards and use the same interface as a regular DRAM chip. The key for exporting a memory board will be to have many solid ground connections between the processor and the memory board so we’ll need to keep them close or just make a double thick S-100 board using a mezzanine connector like we did on the S-100 System Monitor Board. If we maximize the full space available it would give us approximately 100 square inches of PCB space minus the usual ~10 square inches of S-100 overhead for voltage regulators, filter capacitors, mezzanine connectors, brackets, mounting holes, clearance margins, etc.

The main benefit of using the 80386DX is that it meets the minimum criteria for a “sophisticated” operating system like NetBSD or Linux which are both essentially SysV/BSD Un*x derivatives/mutants. AFAIK the minimum requirement is a 32 bit ISA and an MMU with enough address space to hold a rather large kernel and associated components.

The memory 16MB addressing limit of the S-100 bus would be possible in theory to hold Linux or NetBSD but would be extremely limiting in my opinion unless we were seeking a mini Linux like Freesco. We should strive for as large a memory space as possible and I believe 256MB (28 address lines) is a realistic goal using a pair of 128MB DRAM SIMMs. However, this would require at least 24 true address lines being multiplexed to DRAM A0-A11 and 8 individual separate CASx/RASx pairs. To get the density we will need, I think DRAM is the only realistic option without resorting to hobbyist unfriendly large SMT devices. Also we can add a pair of 27C1024 16-bit EPROMs for a full 32 bit data path to the boot ROMs.

This is an enormous project and I recommend starting with a relatively low CPU speed like 4 MHz as a starting point. Once the basic hardware is working identify the bottlenecks one at a time and gradually increase the clock speed. John is well familiar with this technique since all the CPU boards to date have gone down that path.

Thanks and have a nice day!

Andrew Lynch

From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of John Monahan
Sent: Wednesday, July 11, 2012 1:12 AM
To: n8vem...@googlegroups.com
Subject: [N8VEM-S100:914] An 80386 S-100 Board.

Hi guys. Having just finished our 80286 S-100 master/slave S-100 board, see here:-

http://s100computers.com/My%20System%20Pages/80286%20Board/80286%20CPU%20Board.htm

I am thinking how to do the 80386 S-100 board. In a sense it’s easier from a hardware perspective since the jump from 8086 to 80286 in more than 80286 to 80386. As we know the 80286 is really just a fast 8086 (and was used as such).

The 80386 really was a new breed and could run some decent software. That is why I would like to make a new S-100 board. Since the 80386 has a 16 bit access pin it’s easy to have it address the low RAM on the S-100 bus. It would behave like the 80286. However to take advantage of the 32 bit data bus and address lines I’m thinking of having a daughter board with an over the top connecting cable for all that extra RAM capacity.

The question is; should I use static RAM or DRAM. Static RAM is easy to interface, but even with SMT chips lower capacity. With DRAM SIMMS we could have a decent Linux going.

My question to this group is does anybody have a suggestion for a good refresh controller chip/circuit. It’s particularly tricky because sometimes the CPU will not have access to the bus and will be held in its reset state, (Another CPU is running the S-100 Bus). Alternatively anybody know about “Pseudo Static RAM” chips. Apparently these are self-contained with their own internal refresh. Don’t know how they are accessed.

Any suggestions/directions…..

John