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V3 Dual IDE/CF S100 Bus board initial checks



I'm checking in with a progress report and to say thank you John for the board and the mailing to all of us. And thank you Gary for burning the GALs and mailing them to me.

This v.3 is my first experience with the IDE/CF board. I've installed all the non socketed parts, verified voltages and then the two GALs. Rather than use my front panel or non existent monitor board (except a CCS Z80 CPU more on that later) I assembled and ran this small program on a stock (except the disk I/O) Altair 8800b to exercise the ports.

                ; jha 6/27/2015 testport.asm
                
; test the S-100 IDE v.3 port addressing
                
;
 
0100                   org     0100h
 
0100 DB30              loop:   in      030h
 
0102 C30001            jmp     loop
 
0105                   end

Before I run the program I clip on the logic analyzer of my S-100/N8VEM extender to pin 23 of GAL 1 ADDR_8255* it's HIGH. I run the program and I get a couple visible cycles/pulses then the HIGH and LOW lines are cycling so quickly I can't see them cycle anymore. The LOHI and HILO transition leds are on too. <pause> May as well put a scope on it. I've got a pulse width 480ns at 100khz. I'm not seeing it on the 8255 pin 6 CS*

Looks good right? I'm a bit curious about the initial ?settling? time when I first start the test program. I'll move on to some of the other tests I see in the v.2 notes.

Has anyone, maybe Bob Bell, ever run the MYIDE ROM on the California Computer Systems (CCS) 2810 Z80 CPU? 

Does anyone have a system generated for a CCS 2810CPU, CCS 2422 floppy controller and the IDE/CF card?

 - jeffa KF7CRU @jhalbrecht / @TheRetroWagon