Re-wiring the circuit gives no noticeable difference. I see between 40 and 50 ns delay of release of data after pWR* going high. I don't know if that is enough or not. I attached a typical trace here. If you look at pages 331-337 of Wilcox he discusses the circuit and the issue with write. The circuit is not the same as in the schematics on page 494-495 as the logic and path lengths have been changed. I am not sure what to do - the console I/O and serial I/O are working fine but I am not sure on the IDE board yet - I need to but the logic analyzer on the 8255 or IDE port and look at what data is being put on the ports and make sure it matches what I am sending. I probably have a couple of days of debugging here so if you want to wait on pushing the design out until I have the IDE board working with it, I would feel more comfortable.
Also in your write up in the end you state that jumpering P2 3-4 makes all S100 bus I/O have 2 wait states - the way I read the schematic you are adding 2 wait states to M1 pgm fetches. I think you want to jumper 4 to 1 or 7,9 for 2 waits on I/O accesses. Look at 479 as it gives several examples as how to set the jumpers.
The net of above - no matter what frequency you run at, U37, U38, U42 and U40 (if you can find one) need to all be F logic. The state machine is independent of processor frequency (I think Pontius found that in his bring up and is in his reference notes on the wiki).