From: Rich Leary <richa...@gmail.com>
To: N8VEM-S100 <n8v...@googlegroups.com>
Sent: Tue, February 22, 2011 11:20:42 AM
Subject: [N8VEM-S100:71] Re: S-100 Motherboard
So far I have found no issues with the 6-slot motherboard other than
the header orientation issue previously discussed.
What I found with the CPU-Z is that sometimes it would power up OK
with the floppy controller and sometimes not. Once it started it was
OK from then on. I am convinced that the issue with the CPU-Z and the
floppy controller is that the floppy controller (Suntronics UFDC-1
using WD1795 controller) does not have a connection to /PRESET (75).
It does connect to /POC (99) that the CPU-Z generates. I think that
the /POC signal is either too short or not of "good" quality. I am
going to put the scope on the circuitry and check my theory.
My frst attempt at a fix will be to do a cut and jumper patch on the
UFDC-1 to have /PRESET be the source of the board reset signal. I'll
let all know how that goes.
One side comment - the /POC does not bring the monitor prompt up by
itself and that should
happen regardless of whether the floppy
controller responds to /POC. I have to use my RESET button that
grounds /PRESET. /POC clearly does not do everything it should do even
if the floppy controller were to be eliminated or replaced.
In the meantime I will work more with the CPU-Z. The first observation
regards the /POC generation circuit. The circuit on the CPU-Z that
generates the /POC has the usual resistor-capacitor combination but it
connects to a 74LS04 inverter input, not to a 74LS14 with a Schmidt
trigger input. The output of that first inverter goes to a second
74LS04 inverter and then through a 74LS125 buffer to the /POC pin 99.
What is strange about the circuit (other than not using 74LS14s) is
that the output of the second 74LS04 is then passed through a third
74LS04 inverter back to the input of the second 74LS04 with a resistor
network connected to that line and the output of the first inverter
-
some positive feedback to latch the /POC at the high level.
One change I will look at is changing the 74LS04 out for a 74LS14 and
at the same time lifing the lead from the output of the third inverter
that provides the feedback. I need to check what the other three
inverters are used for to make sure they are OK with a 74LS14.
I did bring up the 5.25 inch drives with both CP/M and DOS/65 but they
are being a bit flaky. I suspect that the 40 track DSDD drive may have
a problem but have not done enough troubleshooting to determine what
the issue may be. It might be the drive itself, the cable, termination
(the 1.2 MB drive is at the end of the cable and is the one
terminated), or a chip on the floppy controller.
Andrew - as far as your questions about the 6502 CPU board - yes, I
have my schematics - I just need to find them. :-)
Some more info...
a. Board is reatively lightly populated -
if I were to redo it now I
would put the full 64 KB of RAM on the board as there is plenty of
room and there would then be no need for a RAM board in the system.
b. It generates or responds to most but not all of the standard S-100
signals. Obviously it works with the CompuproRAM 17 and Interfacer 4
and the Xebec adapter for the S1410 hard disk controller. One key area
is PRDY. Both my CPU-Z and the 6502 synchronize floppy I/O usind PRDY.
My DOS-65 IEEE Standard 696 Guide.pdf file (see Peter Dassow's site)
discusses what I did and while it talks about a much earlier
configuration of boards, the logic has stayed the same. The UFDC-1
discussed above is heavily modified to place INTRQ and DRQ on lines
optimum for fast testing by the CPU. One footnote is that the CPU-Z,
RAM17, Interfacer IV, and Xebec host adapter are unmodified.
c. The board has an on-board monitor & boot EPROM - a 2716. The EPROM
actually
contains many key I/O routines both for console I/O, floppy I/
O, and hard disk I/O. These routines are then used by the DOS/65
System Interface Module (SIM) - the DOS/65 equivalent of the CP/M
CBIOS.
d. The first page of the address space for the EPROM is actually where
the S-100 I/O devices are mapped. Said another way - the S-100 I/O
space is mapped into 6502 memory starting at $F800. The useable ROM
space runs from $F900 through $FFFF.
e. Current configuration has the CPU running at 2 MHz. I suspect
higher speed operation with one of the WDC CMOS versions of the 6502
is possible but when I built the board all that was available was the
1 or 2 MHz NMOS version. Glue logic for higher speed operation may
need to change or be replaced with 74ALS hardware or some simple GALs.
That would be an area of fun experimentation and testing. I doubt if
much higher speed operation of the current wire wrap board is
possible
simply due to the lack of a ground plane and the variability of the
wire wrap runs. Clearly a PCB would be better for higher speed
operation.
I am sure there are other aspects of the board I am forgetting. Let me
know if there is something I did not address.
I will look for the schematics. When I find them I'll do a quick check
and make copies to send off to you.
Rich