Rich are you referring to the V1 or later V3 Dual IDE/CF board. On the web page
I used Open Collectors 7403’s with 680 Ohm pull-ups for the Read, Write and Reset signals on the V3 board. Seems to work fine for me. Been using them, (2 boards), for 2 years now.
From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Rich Leary
It is puzzling. I am using all 74LS except the two 74S03s and have tried both NMOS and CMOS varieties of the 8255.
I have gone back to the CF and IDE specs and looked hard at the signal level specifications. My preliminary look seems to conflict with the build notes.
The CF spec defines three type of signals at the interface and one of them (Type 1) does specify a 4V Vih for some signals. Other signals use either 2.0V or 2.8V.
What is confusing is that the Type 1 signals are the address lines (An) and the data lines (Dn). The IORD, IOWR, and CSn (chip select n) lines are all Type 3 and the card inputs for those lines only require Vih of 2.8V to trigger the Schmitt Trigger that Type 3 uses. But the IORD, IOWR, and CSn lines are what are driven by the 74S03 or 74H03 ICs on the S100 board. RESET is a Type 2 signal and Vih need only be 2.0V.
The only on-board pull ups are those associated with the 74S03 or 74H03 ICs and they are very low value. The schematic shows 680 ohm but the notes suggest something like 330.
What is also important to note is that the CF card input leakage current is very low at +- 1 uA so whatever is driving all CF lines is doing so at a very low load level. Since the IDE An and IDE Dn lines all connected to the 8255 ports that probably explains why those lines may be OK. In my Toshiba TMP82C55A datasheet it shows a Voh of Vcc-0.8V for Ioh of -100uA. As long as the load seen by the 8255 is just one of two CF cards with a total leakage of +- 2 uA that would work. But any 8255 outputs driving TTL inputs may have a low or marginal Voh at least for Dn and An.
I can see no reasons for use of the high power - high speed gates and the low value pull ups on the IORD, IOWR, CSn, and RESET lines. As I read the specs it looks like those gates can be 74LS00's with no pull up or much higher pull ups (50K ?). In addition if we do not need to switch the higher currents associated with the low value pull ups that will reduce noise levels on the board.
I need to read the CF spec again and do a line by line gozinta versus gozouta analysis before reaching for the de-soldering braid and solder sucker. It is possible that I have completely misread the spec and if so I apologize for the confusion but right now I think there may be some low-hanging fruit that should be harvested. Even if what my initial look indicates proves correct there may be other issues.
I will get back to everyone hopefully by late on the 18th.
If anyone has reason to show me the error in my thinking please fire away - at my age my skin has absorbed many blasts and a little more will not hurt.