Hi! Thanks! I found that if each populated slot contains 64KB of addressable memory then the decoding is simplified because all you need is the “slot select” signal. The “page select” signals only really come into play when dealing with a slot with less than 64KB memory such as a 16KB or 32KB cartridge. If the cartridge is 64KB then it too can just ignore the “page select” signals and use the “slot select” for the whole thing. What’s neat about the MSX memory bank switching design is that it forms a 4x4 matrix of 16KB blocks. Since the slot select and page select are both based on the state of A14 and A15 and the contents of PPI port A, the CPU can see four of the 16KB pages from any combination of slots you choose. The slot select and page select are done in parallel and they are computed dynamically “on the fly” based on the addresses on the bus. It is a really interesting design that’s for sure! It turns out adding the 32KB SRAM chip in the system slot (slot #0) costs a chip but to narrow the decoding requires another chip (I think). So we get a 32KB SRAM basically for “almost free” PCB real estate wise. There is a spare 74LS08 available so we could generate CS01* for prototyping purposes without a problem. I tell you what though, you’ve got a good idea. How about this… I will put a 3 position jumper on U16 pin 20 so the builder can select either decoding approach. One way has 32KB ROM and 32KB RAM and the other has 32KB ROM only. Regarding the ROM BIOS, that’s where things get tricky. As I understand it the MSX BIOS is copyrighted so we can’t use that. However there is an open source MSX compatible BIOS available. Dan helped us on the N8VEM N8 by using a modified CBIOS as a loadable image to provide some measure of MSX compatibility. http://cbios.sourceforge.net/ Here is where things get really perverted. Hang on to your hat it is going to get strange… Rather than using any MSX CBIOS in ROM I propose to do the following instead: make CP/M 2.2 a loadable from boot ROM image and reserve the CBIOS as a loadable option. Basically the builder makes the board, installs it in their system, turn it on and *BLAM* it boots directly into CP/M 2.2 from ROM drive (and 32KB A: RAM drive) just like the N8VEM SBC and/or N8 do – no hassling with boot media. Straight to the UART serial port or using the VDP display screen as a terminal and use the matrix ASCII keyboard for input. CP/M 2.2 is 100% open source so there are no copyright issues to deal with. Boot floppies are the bane of vintage computer and hobbyists alike. Then if you want MSX compatibility you load the CBIOS from ROM drive or secondary storage and you are off to the races. Alternatively, you skip MSX entirely and load a debug monitor, Turbo DOS, CP/M 3.0, OASIS, or whatever tickles your fancy. Everybody wins! I hope this makes sense and is understandable where I’d like to go with this project. MSX is good but a board that can help *every* builder boot strap their systems *with nothing else* is even better. I uploaded new schematic and PCB layouts to the wiki. Please review and let’s discuss more. Thanks and have a nice day! From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Ants Pants Hi Andrew, yes, you are correct we have a classic SR* NAND latch with U21.. sorry i must have been somewhere else while posing that, i have exactly the same setup, except the Q output from the latch (pin 3 in your example) im not inverting it going into U8 (in your example), im taking the Q output from the "RESET*" NAND.. this would save us an inverter.. ? not too important.. but hey. yes U35 and U34 are redundant.. save us some precious board real estate :-) with respect to U22B outputs, i see different configurations for ROM, RAM etc pages setups all across the numerous MSX manufacturers tech manuals for different requirements. i see you have U35C,D and U36A to add a page CS12* for use by cart slots, then with the 32k ROM you have used A15 and 1Y0*. and we have 32K RAM beside the 32K ROM, do we need the 32K RAM there in slot0 when we have 64K RAM in slot 2? the bios on startup is going to search for the largest chunk of memory anyways, and map RAM into the highest 16K address space via the 8255. one could always use a expansion mapping scheme with Slot2 or 3 to give us more than 64K RAM? i.e. to give us some flexability could we have the 64K RAM onboard and one could always use an expansion in a cart slot to add extra memory .. anyways back to what i was wanting to say.. could we use an 1/4 74LS08 connected to U22B pins 12 and 11 to give us a CS01* and connect this directly to our 32K ROM CE and OE (of the 32k ROM) connected to U22A pin 4 (SLOTSL0) or 1Y0* in the schematic. this way we could loose most of U23C,D and U15D. im still yet to figure out exactly what the Z80 sees while running a cartridge, but i think is usually the lower 16K for BIOS (or maby 32K) the next (moving upwards) for the Cartridge, and the top 16K for RAM. with respect to the 682's, yes is agree. have we put any thought in the BIOS we are going to employ? anyone else have any thoughts on a BIOS? Kind Regards, Antony Hi As you may already know, at the N8VEM project we are working on an S-100 VDP. This board has a V9939 video display processor and a AY-3-8910 sound generator which should allow us to have some MSX2 compatibility when combined with a backplane, S-100 Z80 CPU board, and a memory board. There are more IO and memory features necessary for full MSX2 compatibility required though. I am considering a designing a board to provide the balance of MSX2 functions so that the combination of an S-100 backplane, S-100 Z80 CPU, and S-100 VDP. I envision such a board to be composed of SRAM memory, a couple of 8255 PPIs, a card slot plus whatever extra IO and memory we need. If anyone has detailed MSX2 experience and would like to help out on designing an S-100 MSX2 compatibility board to complement the S-100 VDP please contact me. S-100 and MSX seem like a neat combination but no one has tried it AFAIK. Thanks and have a nice day! -- |