Hi John! Thanks! Yes, I agree and that is the plan once we get the huge bugs shaken out of the prototype board. I am thinking we need some kind of PHANTOM* functionality and also use the upper address lines (A16-A23) to find a spot in the S-100 memory map and coexist with other boards. However, the Z80 CPU is going to want to use code at 0000H-FFFFH so it is going to prefer the lowest block of memory. I am thinking most of the basic S-100 CPU boards are going to as well. Thanks and have a nice day! From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of John Monahan Guys, somewhat related I have opened up a tread with an MSX Forum group that may be able to help us with the related VDP board, and may in fact be able to help here also. To get directly to the relevant tread try:- Also Neil, in the end it will be very useful if this utility board can sit silently in an S-100 system until called upon, since many users will want to do other things with their system as well. Why can’t one boot up with our Z80 board, initialize the 8255, load MSX code to low RAM, jump to it and from there shadow out the Z80 onboard ROM (send 01H to port D3H), giving the full 64K of RAM to the Z80. John From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Andrew Lynch Thanks Neil! That's great news! I knew this board was going to be a tough one. It looks like I munged the reset sequence in translating from MSX to S-100. Hopefully it is fixable! Thanks and have a nice day! From: nbreeden <nbre...@me.com>
I've been looking in detail at the Goldstar implementation Andrew based the utility board on and have some observations and thoughts on how the Goldstar MSX2 design works. The system on power up or reset needs to be able to access the system BIOS ROM; the ROM is in SLOT Zero starting at address 0x0000. The 8255 PIO is also reset at power up or on system reset resulting in the ports being set to input; this means Port A is not configured to allow access to the BIOS ROM in slot zero; the first few bytes in that ROM configure the 8255 to allow it to control the slots. ; $0000 CHKRAM ; Initialize memory bank We thus have a chicken and egg issue. In the Goldstar design U32A and U32B are configured as a set/reset flip flop. I believe this flip flop is the key to how the system powers up; the sequence would be: Reset 8255 ports are set to input The S/R flip flop holds the G inputs on U27 (74LS153) high; as both G inputs are high the two outputs (1Y and 2Y) are low. These two outputs become the select inputs on U11 (74LS139). As A14/A15 are low (these to the G inputs on the LS139) the outputs of U11 that control slot 0 are low and the system can access the BIOS ROM to run the first few instructions; these run and the 8255 is set to configure the slots. Y5 which is generated by the C port in the 8255 as part of the keyboard scanning; this then clears the S/R flip flop; the G inputs on U27 are set to 0s and the system enters the normal 8255 controlled slot mode. The utility board design is using the 8255 select bit to clear the S/R flip flop; I don't believe this will work as it will reset the S/R flip flop before the 8255 is fully configured. I'll be updating my monitor to configure the 8255 as the MSX2 BIOS does and will see if I need to tweak the utility board to match the Goldstar design. -Neil -Neil -- -- -- |