Thanks for your thoughts, Roger. I’ll have to do some thinking on your ideas and see how this chip might be used in the ideas I am formulating.
BTW – the LS670 has Tri-State outputs, so no need to be concerned with pull-ups using this one.
Another question on this topic for those who have already implemented banked CPM3:
The 32K/32K and 48K/16K split has been mentioned several times. Obviously I would think the 48K/16K split would be best from the standpoint of the largest TPA.
But does this put any serious restrictions on the OS?
And is there any practicality to splitting it to say, 44K/20K if there are serious restrictions and more room is needed for the OS in the common area?
Or are odd-ball splits (i.e. not on major memory boundaries) not possible?
Hi Bob --
You might be able to fake an MMU for the 64k address space of the Z80, and do bank select without jumping into the extended addresses of the S-100 bus. Take a look at the 74LS170 or the 74LS670. These are chips that look like four 4-bit registers. You could use one of them to address 16k or 32k chunks of a 128k x 8 SRAM or a 512 x 8 SRAM, and have them appear within the Z80's 64k. Just remember that both these chips are open collector, so you will need to put pull-ups on the Q outputs in order to see the bit patterns that you expect to see.
I've often wondered about building an S-100 card with one of these chips onboard to provide an extended address space. Maybe use a 74LS682 (or similar) to decode the MS 6 bits for access to the registers of the LS[1,6]70, and have various parts of an SRAM chip much larger than the Z80's addressing capabilities show up in the "normal" Z80 address range? One of those 512 x 8 SRAM chips could supply sixteen (aha ... 4 bits!) 32k x 8 pages. You could move 32k pages in and out by writing to the registers in the LS[1,6]70? I'm no electronics whiz, but maybe somebody else could work out the details?
But then you are in the realm of segmented architectures. Why not go with an 8x86 CPU, and give yourself headaches that way?
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