A banked CP/M 3 implementation requires 2 memory regions:
1. Common. This region is in high memory and extends to the top of logical (64KB) address space. Depending on how much memory CP/M 3 needs for common data and drivers this would typically be 16KB or more.
2. Banked. This region starts from location 0 and extends to the base of the common area and gets switched between several banks (typically two, TPA bank and the system bank) depending on the implementation. The size depends on the size of the common bank.
Typical banking schemes are 48 KB banked with 16 KB common or 32/32 KB.
CP/M doesn't prescribe how the hardware implements banking beyond separating logical memory into the two regions and being able to swap out the banked area without impacting the common area.
MP/M takes this scheme a bit further and uses multiple memory banks to implement a multi-tasking and multi user system.
The actual implementation is done in hardware either by the memory boards themselves (using a bank register and logic to implement the common area) or through the use of flat addressing and a memory management unit on the CPU board.
The Z180 has an inbuilt MMU and is my favorite for this reason.
You will need to take a look at your CPU and memory boards to see what logic is available. Some memory boards (such as the Expanroram) used a PROM to implement banking others used discreet logic.
I hope this helps.