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Re: [N8VEM-S100:5375] Z80 CPU board - D2/D3 port timing problem

Hi Philippe,
I've been looking at the timing diagrams you posted, particularly the last diagram, the time delays here are very small in the region of 50-100Mhz (20nS-10nS) and at the limit of 74LS parameters.
My initial thoughts would be to suggest you match the chips used on your board to the types/series suggested by John on the Z80 CPU board page as per the mods for 10Mhz operation and then re-capture the waveforms.
All 74xx chips are 74LS, except the following which are 74Fxx:- 
U2,U3, U12, U8, U4, U23, U25, U38, U39, U40, U45, U30,  U35, U22 and U21.

I populated my board as above and it seems to run fine at 10Mhz in partial latch mode, I have not noticed an instability or crashing when running Borland Turbo Pascal in CP/M 3.0 banked mode.
David Fry

On Sunday, October 19, 2014 7:20:43 PM UTC+1, Philippe Elie wrote:
I looked at this issue again today without understanding how to fix this. One thing is clearly odd : U27 (74LS139 used to generate the chip enable for the D2 and D3 ports) demonstrates a significant delay between O2/O3 ouputs and the E input. in particular, the D2 enable glitch happens even after the E is back high. I tried to replace the chip suspecting it may be faulty, with no success. May be I should try using a F or a HC ? I checked the contacts, solders, etc 
If the timing was so sensitive, I guess some other folks here would have experienced the same issue. but the board seems to work reliably for the group members. Or maybe no one is using the latch mode (P39 unused) ?

your thoughts will be very welcome