[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [N8VEM-S100:5375] Z80 CPU board - D2/D3 port timing problem

I investigated this a bit last night, and identified more precisely the timing issue, while not finding a real fix yet, below some diagrams that illustrate this : 
- timing below is OK (when P39 not jumpered, so no latch), we see one IO on port D3 followed by one on port D2 (part of Monitor initialization):

- timing below is KO (one similar in size with the above, one zoomed), we see the glitch enabling port D2 at the end of D3 access : 

so it seems that either U22LE falls too quickly or sOUT is too long resulting in a short period where U27-1 (enable pin) is active while A0 changes from 1 to 0 after IO access to port D3. This triggers by error port D2 (a quite short 15nS pulse) that apparently is enough to write the wrong data in the register. 

what do you think?