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RE: [N8VEM-S100:1815] S-100 68K CPU board V3

Since this arrangement for these and future 32 S-100 CPU boards will be almost essential could, I suggest we use a better name than “over the top” for this ribbon cable connection.    Could we call it an “Extended S-100 bus”. 



In an effort to keep the number of lines low I have the following arrangement for RAM/DRAM for the 80386 board.  It should also work for a 68K or most other CPU’s.  P5 are address lines, ADS being the strobe/latch signal. On P6,  S100_SEL* is low if the CPU is talking to an S100 bus board, DB_WAIT is high if the RAM/DRAM wishes to add wait states to the parent CPU bus cycle. DB_PHANTOM acts like the S-100 bus phantom line and inactivates the RAM on the Extended S100 bus board if jumpered, CLK is the S1=-100 bus master clock.  M & IO are CPU memory or IO cycles, W/R* read/write cycles.  Finally 80386_RESET is the general S-100 bus reset line.


It should be possible to configure other CPU’s to use this format that different RAM/DRAM boards would not have to be fabricated.  I did consider a shared Extended S-100 bus so multiple CPU’s could share the bus using master/slave/DMA etc. however that really increases the complexity quite a bit. Using the 16M of common S-100 RAM should be good for most applications.











John Monahan Ph.D

e-mail: mon...@vitasoft.org

Text:    mon...@txt.att.net



From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Andrew Lynch
Sent: Wednesday, August 14, 2013 8:27 AM
To: n8vem...@googlegroups.com
Subject: RE: [N8VEM-S100:1815] S-100 68K CPU board V3



On the S-100 80386 CPU board there is a special connector “over the top” for memory boards with full 32 bit addressing and 32 bit data width.  The S-100 bus serves for accessing base memory and IO mostly since it is limited to 24 bit addressing and 16 bit data width.  The S-100 80386 CPU board can work with just bus memory but is limited to 16MB of 16 bit wide memory and is going to be slower than with the special memory board.


Assuming we move forward with a more advanced 68K series processor (68020, 68030, 68040, etc) on the S-100 bus I recommend a similar approach if not the same “over the top” memory boards to make them more economical and provide a useful amount of RAM to more powerful CPUs.  I was considering using the PAK68 approach for a 68020 or 68030 CPU socket mezzanine board for the S-100 68K board but in retrospect it would probably be better to design a new board instead.


Thanks and have a nice day!

Andrew Lynch


From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of yoda
Sent: Tuesday, August 13, 2013 3:09 PM
To: n8vem...@googlegroups.com
Cc: cct...@classiccmp.org
Subject: Re: [N8VEM-S100:1814] S-100 68K CPU board V3


Not sure it makes sense on an S-100 board as the address space is limited to 16 MB.  It will probably be an SBC with a couple hundred MB of memory - when we start getting in the GB range it is not quite as practical and the old chips are limited to 4GB anyway without a lot of additional memory decode tricks.  I can probably get old version of NetBSD flavor running on even a 68K with some tricks - at least I will be able to gauge the complexity.


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