Thanks Roger, I have figured it out. If 128K, line A16 does the two 64K pages, Address line A15 does the 32K within these. Using an AND gate, A15 and a page 1 or 2 signal you can control A16 so that the bottom or top 32K is common. Wastes 32K of RAM but fast and easy! So it looks like I could get CPM3 on the board!!! John. From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] John -- >> The board has 60K RAM, 4K ROM, IOBYTE port and a Z80/S100 bus circuit. The board actually has 128K of RAM (2X64) Use a single 512x8 SRAM chip and a 74LS670. I've built an Z80 SBC prototype with the 670, and I think it would be easy to set one up with either 16k or 32k banks (user selectable) with just a few jumpers. With 32k banks, the CPU would use the whole SRAM chip, with 16k, just half. Worked great on my SBCs, at 10MHz. Both banking schemes seem to have advantages and disadvantages. -- |