John, I have banking hardware being built into my updated (Version 2) Mem8Plus board. It uses 4 chips, (5 if you count the 74LS688 I/O port address decoder) including a GAL22V10. I know you are trying to stay away from GALs on this, but it provides so much flexibility, including dip-switch or jumper selectable common sizes of 8K, 16K, 24K and 32K, normal “Cromemco-style” linear I/O port bank select of up to 4 banks, or encoded bank-select that can be used for up to 16 banks. It also has outputs that can be used to enable a ROM address decoder for the time just after reset when the ROM is to be enabled, then disable the ROM when the first bank is selected (presumably by the CP/M boot loader). And it has a disable in case the CPU has 24 bit addressing and the MMU is not needed (a function I imagine you won’t need.) I have this running on my Mem8Plus V2 breadboard and I expect to be starting prototype board layout this weekend. Bob Bell From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] John -- >> The board has 60K RAM, 4K ROM, IOBYTE port and a Z80/S100 bus circuit. The board actually has 128K of RAM (2X64) Use a single 512x8 SRAM chip and a 74LS670. I've built an Z80 SBC prototype with the 670, and I think it would be easy to set one up with either 16k or 32k banks (user selectable) with just a few jumpers. With 32k banks, the CPU would use the whole SRAM chip, with 16k, just half. Worked great on my SBCs, at 10MHz. Both banking schemes seem to have advantages and disadvantages. -- |