Ah, yes, I remember studying this approach several months ago, I just forgot what you called it and what board I saw it on. I dismissed the approach at that point, as I have several other CPU boards I am using and they are strictly 16 bit address bus. (CCS and Ithaca Audio) My design will work with all my CPU boards, and, I think, many others with no memory management. Further, the MMU is a separate section of my board, directly drives A16 – A23, and I intend that it will work with any memory board with extended addressing capability. Bob From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of John Monahan Address shifting is a very different approach but must be done on the CPU board. See here:- http://s100computers.com/My%20System%20Pages/Z80%20Board/Z80%20CPU%20Board.htm John From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Bob Bell Thanks, John! All the information you provided is great. Much of what you provided I have seen already, but I’m just not able to remember where. I am designing a memory manager to include on my re-designed memory board being built specifically for 8-bit machines targeting CPM3. Since I have been a Cromemco and CCS user for many years, I’ll be using the Cromemco/CCS approach where there are 8 possible banks. However, I thought I had read somewhere that CPM3 supports up to 16 banks. In all practicality, I think 8 banks is plenty, but using 2 x 512k static RAM chips provides the possibility of 16 banks. In the last 24 hours, however, I have done enough of the design to realize that doing 16 banks max is more difficult than 8, and since more than 8 banks is not really practical, I will forfeit that possibility for now. At this point, I will have two RAM sockets for one or two 32K (although 1 really doesn’t make sense for any version of CPM), one or two 128K for 2 or 4 banks, or one or two 512K chips for 8 or 16 banks, realizing that 2 x 512K chips will only utilize one chip (so why put 2 on the board?) My approach is to synthesize A16 to A23 via the bits from the bank select port (port 40 in Cromemco and CCS). Depending on how large I want common memory to be (typically 16K or 32K), and which bank is selected, the circuit will alter these high-order bits appropriately. I am doing this design with GALs from the start. You mention address line shifting - is this the same as the Cromemco/CCS method I am utilizing? Bob Bell From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of monahanz There is almost no practical upper limit Bob if you use the Address line shifting hardware approach. The S100 bus has 24 Address lines (16MB). If you switch RAM banks by switching in/out RAM cards via a hardware port, in theory 8 bits X RAM card size (I have not seen all bits/256 hardware). However again this is way more than you would need. See here for more info:- You can run a non banked version of CPM3 in about 60K or less, however two banks are the norm, more banks are really only used for disk buffering/speed.
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