Thomas, you have to be careful with some of the older S100 bus CPU boards, some float the high address lines for I/O ports and assume the software will always just use the lower 8 bits. For the original 8080 that was fine, but the Z80 In A,(C) instructions use upper & lower. When you come to the 8086 family (and other 16 bit CPU’s) you have to define the upper 8 bits. Since the ZFDC was made to work with MSDOS etc. they are onboard. You need to determine why you are not getting a low on each of the upper 8 lines. Solder bridge, bad driver, dirt on your S100 bus/pins etc. Are you using the SMB V2. It has an option to force these lines to ground. John From: Thomas Owen [mailto:thomasbr...@gmail.com]
Sent: Friday, September 26, 2014 12:20 PM
To: n8vem...@googlegroups.com
Cc: mon...@vitasoft.org
Subject: Re: [N8VEM-S100:5266] ZFDC Initial test questions - failing with possible timing issue? John,
You were correct. The problem was one address line on the 'High' address decoding 74LS682 (A12 actually). By bending out that pin and tying it low the circuit now tests like it should.
Why my IDE board, which uses the same High Address decoding scheme works, and this one does not, is a mystery.
I have a newer Compupro Z80 board on the way and will be interested to see if the problem is cpu related.
Thanks again for your advice.
Thomas
On Thursday, September 25, 2014 5:57:51 PM UTC-4, monahanz wrote: Thomas I suspect you have a problem with the I/O port high address lines (u23 pin 15). Bend out that pin, jumper it to ground,, make sure SW1, 7 is closed, and try again. Bending out pin 2 of U22A and tying it high or low do you get the correct bit 0 values when you input the port. John From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of Thomas Owen
Sent: Thursday, September 25, 2014 1:42 PM
To: n8ve...@googlegroups.com
Cc: mon...@vitasoft.org
Subject: Re: [N8VEM-S100:5266] ZFDC Initial test questions - failing with possible timing issue? John,
I appreciate your reply...
This select circuit is pretty much the same with just a few minor difference as on my IDE board and it works perfectly. The problem is in the signal coming from U19. I have verified the switches on the high address side, bent pins and tied things low, and I still get the output at pin 12 of u19 occurring at the wrong time.
Pin 12 of u19 goes low, yes, but at the wrong time so the gate supplying low to u16 never goes low.
I have tried 2 different cpu cards - Cromemco CPUZ an IMSAI 8080. Both of these work with my IDE card fine.
It seems so simple but when I have my logic analyzer on it I can only scratch my head...
Regards,
Thomas
On Tuesday, September 23, 2014 8:59:07 PM UTC-4, monahanz wrote: Thomas things are definitely not right. pDBIN and sINP must both be working for your system even to signon. You absolutely should be able to get data lines D0-7 to appear on pins 2-17 of U16 – it’s a simple circuit. Back to my original question. Is pin 19 of U23 going low. Is “High-Addr” from U45A pin 19 going low. What Z80 CPU are you using. I hope you have the high address lines low. Is U19B pin 12 going low. Bend out the pins (2-17) of U16 and show that data on the input appears on output of the LS244. John From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of Thomas Owen
Sent: Tuesday, September 23, 2014 2:07 PM
To: n8ve...@googlegroups.com
Cc: mon...@vitasoft.org
Subject: Re: [N8VEM-S100:5258] ZFDC Initial test questions - failing with possible timing issue? John,
thank you for the reply - the switches are definitely set right - all except 5th from right are open and 5 is closed (corresponding to A4). The input of A0 and A1 to U19 look good on my scope.
The problem is that the inputs to U20 (OR) are about 12 us apart, so I never get the 'pulse at pin 1 of u16".
If it helps, it appears that the output of u21, which is NAND of PDBIN and SINP is "late".
I appreciate all suggestions!
Thomas
On Monday, September 22, 2014 7:02:34 PM UTC-4, monahanz wrote: Is pin 19 of U23A going low, If not wrong switch settings. Are you getting correct address signals to u19 pins 13,14 John From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of Thomas Owen
Sent: Monday, September 22, 2014 11:06 AM
To: n8ve...@googlegroups.com
Subject: [N8VEM-S100:5254] ZFDC Initial test questions - failing with possible timing issue? All,
I have just completed assembly of the ZFDC and have begun the most basic tests outlined by in the build instructions: "Go to your monitor and at 0H in RAM enter: DB, 10, C3, 00, 00 Jump to 0H in RAM. This will have your Z80 continuously input from port 10H. Check with a logic probe pin 12 of U19 pulses low". This was successful "Then check that pin 1 of empty socket U16 pulses low". This was not successful. So, I connected my logic analyzer to the chips in question and here I have what appears to be a timing issue: What I see is that SINP goes HIGH, followed by PDBIN, which gives me the first low I need on the input of u20. The next signal, however, is from u19 pin 12 and is occurring at the wrong time altogether (needs to coincide with u21 out). The result is that I do not ever see a low at pin 1 of u16 (u20 out in the above image). System is a IMSAI chassis with standard front panel, Cromemco ZPU at 2 mhz, Interfacer 3, and Ram 17. Any tips will be greatly appreciated! Thomas --
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