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Ok, I have the CPU board and Memory working with the FP. Had trouble with the FP driving all these chips on a single board, so I put in another buffer chip between the FP and the local bus. Fixed a few other timing issues/errors along the way.
Now, I have some questions about the Phantom line. When another board asserts the Phantom line, boards that respond to this line will prevent their output to the bus. This output is understood to be from the memory map, but is the Phantom LIne suppose to also nuke access to I/O? Next, if the CPU board has Memory on board and an external board asserts the Phantom line, then should the CPU switch it's input from the local memory to the Data In bus? That would make sense to me. Boards that do assert the Phantom line, do they synchronize the Phantom line with memory read/write cycles? or, I mean to say the State of the CPU, ie, is Phantom allowed to be active during a pSync state? (which happens at the start of every cycle). On the 8080A, the Data Out should have the Status Byte during pSync, how do boards that generate phantom allow for that? Thanks, Josh Bensadon |