You are correct. The firmware I'm writing does just that exactly. I'm writing it in 2 files. 1 file is the boot loader, it produces a 48 byte file and loads everything from byte #49 and up to upper memory, then writes a jump to this upper memory to the parallel RAM space just after the instruction that kills the Shadow ROM. The 2nd file is written in upper RAM space, but assembled as a binary file and concatenated with the boot loader using DOS "COPY /b A+B" command.
Step1: Copy ROM to upper RAM
Step2: Write "jump to upper RAM" for Step 4
Step3: Kill Shadow ROM
Step4: (executing from lower RAM) Jump to Upper RAM
The jump to upper ram, is the entry point to my boot monitor, which in turn allows booting to CP/M (soon).
Rich Cini has put me on to the correct BIOS needed for CP/M 2.2 (which has some significant differences from CP/M 1.4).
I'm working the differences in.... and hope that you cross your fingers for me! :)
To: n8vem...@googlegroups.com; crus...@hotmail.com
Subject: [N8VEM-S100:4756] Update on Progress with the 8080 board - Board fine!
Date: Wed, 30 Jul 2014 12:37:20 -0700
Good news, the sOUT signal is OK. I had a wrong connection on my board. Board is now working fine with the small test loop below.
Now will see if I can hammer my Z80 monitor into shape. Since the board does not have a power on jump circuit, will have to have it start at 0H, relocate top F000H then inactivate the ROM in low space. Am I missing something?
Hi Josh solved the I/O problem (see below). Since a few others may be in the board assembly stage I thought I would write up my progress so far for the group!
I am running the board in my “test box” that has no front panel. Just the V2-SMB and Propeller Console I/O. I always start with a minimal system so I don’t “blow out” board drivers etc.
First one needs to remember that unlike the Z80, the 8080 does not treat the upper 8 bits of an I/O port the same way. On our Z80 board (and most others) the upper 8 bits are set ort Zero. Not so on this board. So on all the N8VEM/S100Computers boards (and perhaps others), ports need to be jumpered so that only the lower 8 bits are factored into port addressing. All our boards have this option. Not a nice solution since with 16 bit CPUs the ports appear on every 256 byte boundary. Setting the jumper K3 to 2-3 on the V2-SMB allowed the routine below to work correctly.
The IEEE-696 upper address lines float. This will not allow 696 RAM boards to work unless they are adjusted. Our N8VEM/S100Computers boards generally have a jumper to ignore these lines but again will not work with 16 bit CPU’s. Our V2-SMB has an option to force these address lines to ground when this board is the master but release them for slave/16 bit CPU’s.
Second the board does not generate the S100 MWRT signal. (On front panel systems, it’s generated there). One can be generated on the SMB with the JP11 jumper.
There seems to be a problem with the sOUT signal (s100 Pin 45) on J8. It’s been pulled high all the time – at least on my board. I bent out J8 pin 6 and connected it directly to the S100 bus (bending out the pin connection on the extender board). I will try and follow traces to figure what is going on here.
Minor schematic errors.
Pins 8 & 9 of E2 are switched.
Pins 1 & 19 of I8 and H8 should be labeled D-IN, D-OUT, etc.
Still a work in progress, but wanted to save others reinventing the wheel.
I running into a bit of a problem with the 8080 board. I use this code
BEGIN:0009 3E34 MVI A,'4' ;FOR QUICK HARDWARE DIAGNOSTIC TEST
000B D301 OUT 01H
000D DBEF IN IOBYTE
000F D301 OUT 01H
0011 C30900 JMP BEGIN
I can get a “4” on the screen no problem. But I found no matter what value I have the dip switches for port EF I get a blank on the screen.
With the SMB switches set to 33H one normally see “3’s”
Analysis tracked things down to the fact that sOUT was not being generated on the bus. The LED on the SMB in fact did not flicker.
I bent out pin 6 of J8 and bent out the edge connector pin going to the bus and jumpered J8 pin 6 to the S100 line #45. Now sOUT flickers (as it should). I find that pin 45 on the board is being pulled high (and warming up the J8 IC). Before I dig further, wanted to know if you see this.
SMB, Propeller Console I/O board (Ports 0 & 1) and the 8080 board nothing else in bus.
Note have to generate MWRT on SMB - J11, need to tell people this as it’s not generated on your board if no FP.
I have JP8 LHS jumper open the other 7 closed
JP9 LHS jumper closed all the rest open.
So 8K ROM at 0, the rest RAM
No R15 jumpers so all I/O ports via bus
JP4 1-2, JP1 2-3, JP6 2-3, JP7 1-2
No A5 ,A6 , J5 or J3 (but J7 is present).
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