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Re: [N8VEM-S100:4398] Re: Group Purchase - Z80 CPU V2 board PCB

Correction, I meant Gary

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On Jun 28, 2014, at 11:23 AM, "Monah...@gmail.com" <monah...@gmail.com> wrote:

Thanks for writing that up Alex. Very useful, will add to page when I return from vacation (2 weeks) 

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On Jun 28, 2014, at 11:05 AM, Gary Kaufman <geka...@gmail.com> wrote:

Alex -

The jumpers are a bit different also.

These are my notes which helped me get the system up and running.  The * are the settings I ended up using.
If I have any wrong I'd appreciate hearing from the group!

Z80 CPU Board Jumpers:

JP1    GND to OV_A (S100 pin 20) (normally open)
JP2    GND to OV_B (S100 pin 53) (normally open)
JP3    GND to OV_C (S100 pin 70) (normally open)

JP4    *Reset to POC        Vertical Jumper
JP5     Reset from power    Vertical Jumper
JP6    *Reset to slave_clr    Horizontal Jumper
JP7    *Reset from push button Horizontal Jumper

JP8    EPROM/EEPROM Pin 23 / A11
    1-2    A11    *1-2 for 28C64 or 27C64
    2-3    VCC   
    1-2    VCC    *open for 28C64 or 27C64

JP10    Onboard Rom
        *Jumpered  Enabled
        Open       Disabled

K1      1-2    PWRFAIL to NMI        If NMI software is not implemented do not connect
     2-3    NMI to NMI       

K2     1-2     older pre-IEEE696 boards
    *2-3     clock disable of control lines

K3    CPU Clock Source
    *1-2     Oscillator
     2-3    external CPU Clock (NDEF3)

P2    Memory window configuration port
    0xH to FxH
        A4     1-2
        A5     3-4
        A6    *5-6        Output Ports D2H, D3H
        A7     7-8

P3    PROM Boot Address
    *no jumpers    F000H

P4    *1-2    S-100 2Mhz clock signal to bus when z80 active  Vertical Jumper
    *3-4    S-100 MWRT to bus when z80 active        Vertical Jumper

P8/P9/P10    Monitor Jump Location
    P8      P9      P10
1    U15      GND      A15
2    U15     GND      A14
3    U15      GND      A15
    *F000H    P8 1,2,3,4 to P10 1,2,3,4

P36     Allows wait states
     1-2  Every sINTA
    *3-4  M1 memory bus cycles
     5-6  All memory cycles
P37    *1-2  Partial latch mode    Vertical Jumper
     3-4  Full latch mode        Vertical Jumper

P39  A12 Address Line to U13 (EPROM/EEPROM)

     1-2  Tie to VCC
     3-4  Tie to GND
     5-6  Tie to A12 
    *7-8  Control by bit1 of port D3H

    Output 00H to port D3H to select lower 4K of ROM
    Output 01H to port D3H to totally remove ROM from the Z80's address space
    Output 02H to port D3H to select upper 4K of ROM

SW2    ME Wait states for P36 option
    * switch 8 closed (right most) for 1 wait state, rest open

SW3    I/O Wait states
    * switch 7,8 closed (right most 2) for 2 wait state, rest open

SW4    ROM Wait states for onboard EEPROM
    * switch 8 closed (right most) for 1 wait state, rest open

-  Gary

On 6/28/2014 10:43 AM, mon...@vitasoft.org wrote:
Alex always use the board layout .pdf 's that is always the most current. 10Mhz may not work in your system try 8 and 9 also. Always 2Mhz.

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