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Re: [N8VEM-S100:272] Request For Comments (NIC Board)
I looked over the specs for the ENC28J60 and I have some thoughts...
The chip is interfaced via SPI, which although fast is still a serial protocol.
The chip has on-board dual ported ram which is used for incoming and outgoing packets.
One of the things that slows down protocol stacks is the need to copy buffers around
(something I learned in signal processing).
When a packet arrives, I assume it is placed in the dual ported ram of the ENC28J60,
and can then be copied into the lower 4K at the bottom of the Z80's ram space. From
there it would get copied yet again into the hosts systems space for further processing.
I can see several ways to make this all work better. For one thing I think adding four
interfaces to the card is overkill. If the board could do a really good job with just one,
that would be something.
You have to make a decision about how the board is to be used, and where the TCP/IP
stack is going to live. Lets say you put this board into a Z/80 system in an S-100 bus,
memory is short enough for the master CPU without having a full TCP stack there.
Doing a better job with just one channel might include making the master's window into
the ram space of the on-board CPU the same size as the dual ported ram on the
ENC28J60. Then the master would have access to the entire buffer space. The Z80
on the board could manage the ENC28J60 and signal the master via IRQ or perhaps
with a DMA terminal count condition.
Also the ENC28J60 is a 10base-T interface which I believe is limited to 10mb.
Just some thoughts...
On Jun 8, 2011, at 11:29 PM, mike wrote:
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> Hi All,
> I just sketched out a design for a 4-port Ethernet S-100 card. I likely
> won't get around to producing this for a while since I have enough on my
> plate to keep me busy for quite some time, but it would be good to start
> getting the ball rolling a little bit on something like this.
> In a nutshell, it has an on-board Z/80 that bit-bangs an SPI bus
> inter-connecting 4 ENC28J60 MAC/PHY ICs, and the Z80 has 32K of ram to
> use as scratchpad and buffer space. The S100 master has access to a 4K
> window at the bottom of the Z80s 32K RAM. There is one I/O port for
> communicating comamnds and status between the S100 master and teh
> on-board Z/80. The Z/80 can interrupt the bus master and interrupt
> vector(s) are software programmable.
> Welcoming comments.
> - --Mike
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