Re: CF IDE card checkout and final assembly problem

Hi Thomas,

nice fix :-)

I'm no S-100 bus signalling expert but I would have logically expected the Data lines to be settled and valid at the point in time the WR* signal goes low, this would seem to not be the case in this instance. I don't see this as a fault in the IDE card design but rather that the device driving the card (CPU card) is not performing as we would expect.

Part of the fun of mixing old and new technology perhaps ???

regards

David Fry
On Monday, June 9, 2014 8:27:54 PM UTC+1, Thomas Owen wrote:

UPDATE:

As mentioned, I set up a delay by using the 2 unused gates on the 74LS02 to delay the clock signal to the flip flop. Drive selection now works perfectly.

I will see if I can get a screen shot from the analyzer showing the relationship of DO0 to the clock, but for now, here is what I did:

U15 pin 1 -> U15 pin 5/6 | U15 pin 4 -> U15 pin 8/9 | U15 pin 10 -> U16 pin 3

Thomas

On Sunday, June 8, 2014 7:58:45 PM UTC-4, Thomas Owen wrote:
All,
I had posted this to the thread dealing with ordering this card, but decided to post a new topic dealing with the problem I have had with final checkout of the board.
During assembly the board passed all the 'in progress' checks. The final steps were to output to different ports:

I have output the following and everything passes:

QO33,80 ; Configures ports A, B and C as output ports
QO32,2B ; Selects right hand pair of digits
QO30,01; display 01on right digit pair and work through each bit - all ok

QO32,2c; Selects middle pair of digits
QO30,01; Should display 01 on middle digit pair, work through each bit - all ok

QO32,2d; Selects left hand pair of digits
QO31,01; Should display 01 on left digit pair, work through each bit - all ok

All displays are correct.

Now the final step is the Drive Select and that is where I am having trouble:

Board always comes up with 'Drive A' selected

Now, QO34,0; no change

Reset, start again:

QO34,1; no change

I can never select drive B.

Several generous members (thank you David Fry) have made suggestions, and here is where I now stand:

My preliminary check this afternoon shows me that there is a timing issue at U15, the 74ls02. Using my logic analyzer and monitoring the inputs and the output (which clocks the drive select flip flop) I see a big timing difference between SEL_SECOND and WR.

What this means is that the output of the gate never goes high allowing the bit change to effect drive change/selection.

I am going to get some screen shots from the analyzer tomorrow, and if anyone has any suggestions I would greatly appreciate it.

Thanks,
Thomas