Hi! Thanks Leon! I think the reset latch interlock is a feature not a bug! The S-100 VDP design traces from the ECB Sound and Color Graphics board (TMS9918 and AY-3-8910) and a bit from the N8 (joysticks). In fact our own Tom LeMense and Dan Werner helped with the original design. The reset logic is intentional and part of the initialization routine is to set the latch pins so the bus reset lines are enabled. I forget the exact reasoning but as I recall we wanted the CPU to have control over when the TMS9918 and/or AY-3-8910 could be reset. If the CPU did not initialize the latch then both chips were disabled and output suppressed for sound or video. Maybe Tom and/or Dan can shed some light on the original SCG design. I have no problem removing the reset latch interlock but I’d like to know why it was added in the first place. I just remember all the details anymore! Thanks and have a nice day! From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Elsid Hi Andrew, The problem with the VDP reset circuit is that the BRD-RESET* power on pulse has to go through the U27C AND gate. The other input, SYNTMS* of the AND gate will be at logic level 0 having just been reset by BRD-REST* on p1 of U20. Thus the output of U27 cannot go to logic 1 (which it needs to do to reset the VDP) until you output a 1 on SYNTMS* via the lactch (U20). Regards Leon On Monday, August 13, 2012 5:08:30 AM UTC+10, lynchaj wrote: Hi Leon! Thanks! I believe the V9938 will have to be configured to output its color information on the Cx port. I don’t think it will do it by default but I think it is designed to work with a RAMDAC. The BRD-RESET* circuit should also be able to reset the V9938. What is your setting on K1? It allows either RESET* or SLAVE_CLR* to reset the VDP depending on which is pulled low. Please check your S-100 bus to make sure RESET* and SLAVE_CLR* are pulled high and also what K1 is set to. Then try pressing the reset button and see if BRD-RESET* goes low. What CPU board are you using and how is it configured to export its reset function (RESET* or SLAVE_CLR*)? The SYNTMS* signal was intended on the ECB SCG board to reset the TMS9918 at will independent of the system reset. It is useful to keep in case the V9938 goes insane and the CPU wants to regain control of it. It and the system reset function should both work so if it is not there is something funky going on. Thanks and have a nice day! From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of Elsid Hi Andrew, I didn't get the RAMDAC to respond. I'll have to recheck the test program to make sure I was doing everything right. I got the LM1881 circuit going ok but used the CSYNC output on p5 to drive it rather than COMP_VIDEO on p21. I guess it would work on either. I'll try swapping it to p21 to test. The VDP reset circuit may need redoing as the Power On reset via BRD-RESET on U27C p9 will never reach the VDP. But you can still reset it through the Latch. Regards Leon
Hi Leon! I was wondering if you ever got the RAMDAC to respond during build and test? By itself the RAMDAC would not be sufficient for VGA display but with some additional circuitry in the prototyping area I think it may be possible with the V1 prototype. The key would be to configure the V9938 to output color information on its Cx port. Then the RAMDAC could decode that information and produce “almost” VGA compatible signals. It would still need the final stage circuitry and the HD15 connectors. One signal that is absolutely missing though is VSYNC* and on the V2 prototype it will be (hopefully) derived from the composite video signal using the LM1881 circuit. Even just establishing the V9938 can output color information on the Cx port would be big progress though. I am confident the RAMDAC will work since it does so beautifully on the ECB uPD7220 circuit. Once programmed, the RAMDAC gives a *lot* of flexibility over the display palette and is really a neat device. Also, the V9938 could be tweaked to produce sort of VGA signals using a set of 390 ohm resistors on R, G, and B. Also the HSYNC* comes directly from the V9938 but VSYNC* would again have to be derived using the LM1881 or other means. I appreciate your help on this neat board! Thanks and have a nice day! From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of Elsid Hi Andrew, Sure, I can check things look OK on the new board design. I don't think I ever got the VGA output going. Did anyone else have any success with this board? Best regards Leon Hi Leon and Pontus! Thanks! Remember the S-100 VDP project? I’ve finally found some time to update the circuit to include the AY-3-8910 sound generator, VGA monitor interface, and do some other clean ups. Would you please check out the schematic and PCB layout and compare against your notes from the last prototype build and test? I would like to do another round of the S-100 VDP prototype boards and would like to make sure all the lessons we learned from the first prototype are fixed. Thanks and have a nice day! From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of Elsid Hi Andrew, The additional caps across the V9938 power pins are an attempt to make the video less noisy. They didn’t seem to have much effect. I suspect the noise I’m seeing on the video signal on the CRO may be due to the routing of the power lines for the video amp through the dynamic RAM circuit. (lots of hash from the refresh?) Maybe the video output could be routed away from the RAM and separate traces for the video amp power from the regulator provided. The extra pull up on DHCLK p3 of the V9938 (and cut trace to R53) is there because I was worried that the 5.37MHz output would be doing something to the LightPen inputs LPS and LPD. The 470 ohm pull downs on R, G and B outputs (p22, p23 and p24) on the V9938 are there because I suspected I may have damaged the COMP_VIDEO output (p21) and needed the pull downs to get the internal transistors to drive – the output was OK as it turned out. The reset circuit needs some changes. The V9938 is not receiving a “power on” reset because BRD-RESET* is being gated by SYNTMS* at U27C. (SYNTMS* is reset at turn on by BRD-RESET*). The V9938 has to the manually reset by toggling SYNTMS*. I have tried the FMS6141 video amp configuration and it works fine. Parts of the board working/not working: 1. Address decoding – working but could do with changes to make more MSX compatible – as you’ve said. 2. Reset circuit – only working manually – see comment above. 3. Composite video output – working but noisy – power routing? 4. Video RAM – working – I tried adding in 100 ohm resistor in the RAS,CAS and R/W* lines (like some MSX2 designs I’d seen) to reduce ringing. It didn’t reduce the video noise but it may be a good idea anyway. 5. BT478 – I haven’t tried yet but maybe we can route the RED, GRE and BLU outputs to a header for a DBS15 connector to drive a 15kHz VGA monitor. Best regards Leon Byles
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