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RE: [N8VEM-S100:6628] Re: CPM3 memory banks

Yes, I see what you have done.  I recall several months ago, in response to some of my more preliminary questions on this group regarding bank switching, someone suggesting the use of the 74LS670.  It didn’t click with me then, but I think I see how you used it in your design.  12 chips is a very nice, lean design.  Your lament regarding the 32K/32K split is understood.  I have the feeling that a 48K Bank / 16K Common would be more appropriate for CPM3.  In that respect, I am designing my MMU to have a selectable common size: 32K, 24K, 16K and 8K.  It will provide bank-select for up to eight banks.  Theoretically, it is capable of the CPM3 maximum of 16 banks, but hardware practicalities and a complete lack of need for 16 banks preclude fulfilling that possibility at this time.   Although totally decoupled from my memory the MMU will live on my memory board.  It will be able to function on its own and can operate with the on-board memory or with memory elsewhere on the S-100 buss.  I think this design is turning out rather simple and elegant as well.  So far it has 4 chips, which includes the address decoder for the bank-select port (any one of the Z80’s 256 ports); one of the chips is a GAL.  The RAM on my board will be able to utilize 32K, 128K or 512K parts, 2 sockets, for a maximum of 1MB.  However, 512K is the practical maximum to go with the eight banks.




Bob Bell



From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com]
Sent: Saturday, March 21, 2015 5:58 PM
To: n8vem...@googlegroups.com
Subject: Re: [N8VEM-S100:6628] Re: CPM3 memory banks


Hi Bob --


>> In all practicality, I think 8 banks is plenty, but using 2 x 512k static RAM chips
>> provides the possibility of 16 banks.

Maybe take a look at what I've done?  It is in the "simple MMU" section of my Web site (sites.google.com/site/oldcpusrus).  I used a 74LS670 to extend the address range of a Z80.  It is running now with CP/M 2.2 and one 512 x 8 SRAM giving 16 pages of 32k each.  BUT, I'm having second thoughts about 32k pages.  The way CP/M is structured (with the system in high memory and the base page, and TPA, in low memory) switching banks is tricky.  Maybe 16k pages would work better?  Seems ideal (to me anyway) to have the banked memory in the range of 4000h to c000h??

Anyway, my experiment is running at 10 MHz with a compact flash as "disk".  Seems very solid.  It is quite compact -- only about a dozen chips.  If only I knew how to turn it into an S100 card ......


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