Re: [N8VEM-S100:489] S-100 6502 CPU poll

[Neil Breeden <nbre...@comcast.net>]

Yes, the Beta board has an 8 position DIP switch to set the 256 Byte I/O block and the start of the on-board EPROM address. A8..A15 are configurable via it.  I would assume the re-spin boards will follow the same configuration design

Keep in mind however that the design works as follow:

If A8..A15 match the DIP switch setting then the P=Q output of the 74LS682  is LOW meaning that the current memory address is in the designated 'act as port I/O block'.

If A8..A15 are greater then the DIP switch setting then the P>Q output of the 74LS682 is LOW meaning that the on-board EPROM is enabled. 

if both P=Q and P>Q are high then the system assumes RAM is being accessed. This means that if you set the DIP Switch to all 0s (all closed) the addresses 0000..00FF would be the I/O space, 0100-FFFF would be considered as ROM. There are some config jumpers that allow you to gate A11 and A12 into the mix as well; I haven't used these.

The onboard EPROM is laid out for a 2732. As the 6502 at reset jumps to the RESET vector address (found at addresses FFFE and FFFF) you will typically want to have EPROM in upper memory so the RESET vector is not volatile. Assuming you need the full 4K for the EPROM (F000..FFFF) you would jumper the I/O space at EF00 resulting in I/O at bytes EF00..EFFF then the EPROM mapped at F000..FFFF.

With I/O at F800 (DIP Switch set to F8) it places the I/O space at F800..F8FF, EPROM is then enabled at F900..FFFF which become physical EPROM address 900..FFF, EPROM bytes 000..8FF are not accessible. This is neat way of allowing you to only use the amount of EPROM needed (up to 4K) freeing up as much RAM as possible. Note that when I program a 2732 for the board I end out outputting a BIN file from the assembler; then when I load it into the programmer I manually offset it by 900 (option in my programmer software), If I use Intel HEX files the offset doesn't work; I am assuming because the actual load addresses in the EPROM are in the HEX file.

It took me a few days to wrap my head around this as it's different from the 8080 and Z-80 CPU cards I'm used too.

-Neil

On Nov 24, 2011, at 2:33 PM, lynchaj wrote:

> Hi
> 
> Yes, the IO and ROM space is selectable.  However the ROM monitor code
> is designed to have the IO at $F800-$F8FF and the ROM at $F900-$FFFF
> 
> Of course you can adjust it with your own code or modify the source as
> you see fit.
> 
> The documentation, schematic, PCB layout, and ROM monitor code, etc
> are on the N8VEM wiki here
> 
> http://n8vem-sbc.pbworks.com/w/browse/#view=ViewFolder&param=S-100%206502%20CPU%20board
> 
> Neil was able to get the Apple I software to run on the S-100 6502 CPU
> board and it worked well.
> 
> There is a large prototyping area too so if you want to include your
> own TMI circuitry that's possible and/or your own IO devices.
> 
> Once you get it working though please send the schematic back to me so
> I can roll those changes into the S-100 6502 CPU V2 board.
> 
> I am trying to gauge whether to do a run of PCBs with this version or
> wait until all the features are included.  The wait for V2 will likely
> be months though.
> 
> Thanks and have a nice day!
> 
> Andrew Lynch
> 
> 
> 
> On Nov 24, 4:55 pm, "j....@cimmeri.com" <j....@cimmeri.com> wrote:
>> Can that address space start address be made selectable?
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>> lynchaj wrote:
>>> Hi
>> 
>>> More information on the S-100 6502 CPU board
>> 
>>> The S-100 6502 as a specific range ($F800-$F8FF) of memory mapped to
>>> the S-100 IO space.  You can use standard S-100 IO boards like normal
>>> which you access by sending the 6502 to a specific range in memory.
>>> It works amazingly well and you can use the regular S-100 peripheral
>>> boards like Serial IO, etc.
>> 
>>> http://n8vem-sbc.pbworks.com/w/browse/#view=ViewFolder¶m=S-100%20...
>> 
>>> http://www.youtube.com/watch?v=tgFUeJdO7-E
>> 
>>> Thanks and have a nice day!
>> 
>>> Andrew Lynch