S-100 6502 CPU poll

[lynchaj <lyn...@yahoo.com>]

Hi,
Thanks to Rich and Neil for their hard work, the S-100 6502 CPU is
basically ready to go.  However as it is currently configured, it is a
bus master CPU with boot ROM only.  It does not support the Temporary
Master Interface for multiple CPU bus masters and it does not include
any SRAM or IO peripherals such as serial ports, parallel ports, or
timers.

Eventually, I would like to make the S-100 6502 CPU support TMI and
also include some additional SRAM and IO.  However that is probably
months away.

Would the S-100 builders be interested in a S-100 6502 CPU board V1
which captures the current CPU and boot ROM only?  If there is enough
interest, I could do a production run of these boards and later
include the SRAM, IO, and TMI interface.

Ideas, thoughts, all welcome.

Thanks and have a nice day!

Andrew Lynch