Great observation Gary, thanks. I have been using the 5V chips these days, but have a board 3.3V board running with a 36MHz Oscillator. Nevertheless I will upgrade all my boards to a 74F240. Don’t have 74F139’s but will use 74S139. The latter should be OK since the inputs are buffered and thus no bus loading. As you probably know by now I have been working on a V2 version of that 80386 board. It’s been a very long road with a number of prototypes but I’m real close to a final CPLD driven version now. The fundamental problem with putting the 80386 (and 80486) on the S100 bus is the processor read and write signals come out very early in the cycle. The S100 bus pWR* had to be modified and was on the “V1” 80386 board. However the pDBIN signal is also marginal. I could get a reliable system with a CLK2 of 36MHz (S100 Phi 9 MHz) in a 21 slot Godbout motherboard with active termination, but it was clear this was not optimum. The good news with a CPLD driven board is one can have much more control on the length and timing of these signals. The bad news is – lots of fiddling around with byte, word, even, odd, RAM and I/O read/write logic signals analysis. I’m getting there. Right now I have a solid 40MHz CLK2 board working (S100 Phi 10MHz). This is with your V3 16MB RAM board and with the newer V5 board (also the old 4MB boards). The V5 (GAL based) board, BTW gets around the delay of the above 74xx circuits. Anyway again, great info Gary. Will get you a V2 80386 hopefully soon. John From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Gary Kaufman One board that's been frustrating me for a long time has been the Version 03 16mb SRAM board with the 80386 processor board -- |