Well I have some good news & bad news Gary.
Quite by accident and for other reasons, I popped the 80386 board into my test system using the Cyix 80486-40 rather than the normal AMD 80486-40. To my surprise I found I could not get the SMB V2 with K4 (2-3) i.e. output a bit 0 to a 1 to switch in the 80486.
If you remember the Cyrix is a poor man’s 80486. It’s an 80486 (without the math processor) in a 80386 socket. It runs 80386 code about 10% faster.
What is interesting is that the old SMB V2 K4 1-2 position switched fine and back to the Z80. Removing the K4 and using the Cyrix P32 1-2 & 3-4 also worked fine back & forth.
As Shakespeare said: Something is rotten in the state of Denmark here. I suspect the problem may be on the SMB V2 port and not the 80386 board.
There were some 74Fxx chips on the Cyrix board that were not on the AMD board (have two BTW, both behave the same), I switched these – no difference.
It’s late, so more tomorrow – the goes my weekend!
On yours BTW, remember the SMB V2 LEDs are not monitoring the actual S100 bus lines, they are looking only at the output of the FF, U33. Also remember you are seeing Q* and not Q. The front panel “TMA” LED however does show the S100 bus status of TMA0.
In any event your TMA3* should never light up. This indicates that pin 3 of U33 is going low. My BIOS for MSDOS for the 8086 family uses TMA0*
From the MASTER.Z80 Monitor…
;THIS ROUTINE ACTIVATES THE S100 TMA0* LINE USING THE SMB (SWITCHES COMTROL OVER TO THE 8088, 8086 or 80286....)
;Inputting (any) data from Port SW_DMA0 lowers the S-100 TMA0* PIN #55 line.
;THIS WILL CAUSE THE 8086/80286 BOARD TO BECOME ACTIVE AND TAKE OVER THE BUS.
;THE Z80 WILL BE IN A PERMANANT HOLD STATE UNTIL THE S100 PIN #55 IS AGAIN RAISED.
;NOTE FOR THE NEW V2 SMB WE RAISING BIT 0 OF PORT 0EEH (AND ALSO LOWERS TMA0* FOR THE SMB V1 Board).
;WE WILL INCLUDE BOTH OPTIONS
IN A,(SW_TMA0) ;THIS SWITCHES CPU'S with no block Move
NOP ;Z80 WILL BE HELD HERE
LD A,01 ;Utilize the more specific circuit on the V2-SMB
OUT (SW_TMAX),A ;Make sure its bit 0
JP BEGIN ;WILL DROP BACK TO REBOOT MONITOR
Hope this helps. Will dig some more tomorrow.
From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Gary Kaufman
Thanks David for your "eagle eyes", unfortunately correcting the .1uf -->47pf didn't fix my issue. I've also swapped every IC except the 386, checked every resistor and resoldered very joint.
Good point Dave, C67/R18 is to pull out noise/false triggering from pHLDA transferring control to the slave. (came from an old Godbout board, if I remember correctly). Could be an issue getting back to Z80.
One test you could do is use a completely separate port in your system to flip between CPU’s…
Find a board that has a port in which you can output a bit high or low. Our Parallel Port I/I board is ideal for this. It must be high on reset. We need a spare OC gate. Use U49 pins 11 & 10 on the 80386 board. Disconnect the K4 jumper on the SMB V2 and all jumpers on P36. First check the “O” command then does nothing. Next run wire jumper from a bit on your (new) output port to the bent out pin of U40 pin 11 . Connect the bent out pin 10 of U40 to pin 2 of P36. Also jumper P36 3-4. Lower the bit on your new output port, the Z80 should switch out and the 80386 in. With a logic probe check the levels of pins 11 & 10 of U40.
Next within the 80386 RAISE the bit. The Z80 should switch back in. Again with a logic probe check the levels of pins 11 & 10 of U40.
From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of David Fry
I compared your picture to my board and jumpers are the same BUT one thing I did notice,
Check C67 directly beneath the 80386 chip, have you mistakenly fitted a 0.1UF here as it looks the same type as the cap next to it (C18 which is a 0.1uf)
C67 should be a 47pf and is in the master/slave area of the circuitry.
I only noticed it because on my board the 47pf is blue and the 0.1 next to it is yellow :-)