I have written up the proposed 2 GAL design for this V3 IDE board along with the PALSAM code. It can be seen at the bottom of this page:- http://s100computers.com/My%20System%20Pages/IDE%20Board/My%20IDE%20Card.htm Could you take a look at it and see if the is anything wrong/needs improving before I send off for a prototype. Thanks guys for all the help on this. John From: yoda [mailto:yo...@r2d2.org] Well you won't use all 8 lower address lines because most devices have registers so for example A0 will hardly ever have to be compared and most times A1 will fall in the same category. I will look forward to looking at the write up and logic equations as I can't tell exactly what the signals look like without the equations. Dave Dave I will write-up a completed description of the new circuit today on the S100Compuers/IDE web page with PALASM equations etc. Will let you know when done. I think I will stick to using two GALS. I hate to give up 16 bit I/O port addressing. Really burns me up to see endless blocks of I/O ports duplicated with 16bit CPU’s. Your 74LS682 (+ jumpers) for the upper 8 bits still leaves me with the need for the lower 8 address lines. There are not enough pins available on one 22V10. I figure if I go the GAL route I may as well do it properly and with the most programming capability – at least for the prototype board. Stay tuned John From: n8ve...@googlegroups.com [mailto:n8ve...@googlegroups.com] On Behalf Of yoda John Can you post the GAL file as well - I like the way it looks now (guess I should have read the forum before sending last email to you). I think condensing things into the GAL may eliminate future timing problems and does allow a lot more tweaking if necessary. Looking at proposed schematic without seeing equations, I think you are duplicating function in the 2 GALs. Think about what I proposed in my email. Use a 682 for the upper 8 address lines and use it as input into a 22v10 and then use the lower address lines and other S100 signals as input and derive the necessary signals. The way you have it now it looks like you are using duplicate signals like bsInp, bsOut, etc on both GALs. Dave
Dave, I just looked into using two GAL's (22V10's). With that setup things do indeed look simple/clean. Please see the attached schematic. A few non obvious points. I buffer the S100 signals so only one LS load per input per board (assuming these Lattice LGAL's ate LS loads). This includes data line D0. I added pSYNC to pin 1 of U102 in case the was a need to clock and use registers (instead of computational outputs). The GAL logic is simply the previous signals moved into the GAL. Is my thinking OK on the 74LS373's The only catch with all this is two GAL's instead of one. What do people think? John
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