Hi Charlie, Andrew has passed on to me your e-mail below. I will actually respond in a general way because over the months a number of people have asked about this effort to build a XVGA (not VGA) video board for the S100 bus. Clearly VGA chips are outside the realm of a Z80/64K ram etc but the final vision I have is a XVGA driven S100 system driven by an 80386 or 80486 using Lynix etc. This is a very long story, and way too much for me to detail here. Suffice to say we are now on our 7th prototype board! The old saying "when you are up to your neck in alligators, it's hard to remember the original idea was to drain the swamp! Ok let me get started:- Way back in early 2011, I looked at a number of the popular and common "all in one" VGA chips. Some of the later ones like the Cirrus CL-GD5420 literally had only a half dozen buffers interfacing with the PC ISA bus. The two busses are actually quite similar, both being Intel CPU's based. I figured how hard could it be! Answer, very hard! There were a number of early problems. First source code for the VGA bios (which resides at C000:0) is not available. It's a black box. I had to sidetrack and make an ISA bus equivalent board try various bioses on it (booting from a CGA board) to show that in fact the ROM I had was viable and would initialize the VGA chip at any 1K boundary. I found that simply plunking the chip and ROM into our 8086 driven systems did not work. Long story short, the initialization process in the ROM sends out back to back bytes to the chip (so that it is I assume compatible with the original 8 bit bus PC's). All our 8086 family of boards always send 16 bit data as 16 bits. The Cirrus chip does not lower the ISA lines IOCS16* or MCS16* sometimes -- particularly when initializing. The PC-AT has motherboard circuitry to send the 16 bit data back to back as 8+8. I know of only one S100 CPU board, The TechMar 8086 board that had onboard circuitry to do this. Grossly simplifying it latched the lower 8 bits, increased the address by one and sent both data sets with one RD/WR strobe. As it turns out the PC-AT is more elaborate it sends out a distinct and separate Rd/Wr strobe of each 8 bits of data. This enormously complicates things for high speed S100 bus access. It required a 74LS164 to step the various synthesized in time signals (all the time holding the CPU in a wait state). At first I did all this with TTL gates, then I realized GAL's allow me much more flexibility trial/and error. OK the net result of all the above was I still could not get a reliable video screen. Odd characters would randomly appear -- RAM access errors. So I dropped down to trying all of the above using our 8088 CPU board -- which actually sends 16 bits back to back as 8+8. Again it did not work reliably. Unknown was the fact that the 8088 does not have a few 80286 op-codes, but even the NEC chip failed. I then switched over to Sergey's XT 8 bit video board. That definitely works with only an 8 bit bus and uses the Trident TVGA9000 chip. Still could not get solid video. Frustrating is the fact that the ROM is visible on these boards, an OK but you cannot checkout the RAM. At this time I lowered my sights and started with the old PC CGA board in the ISA/S100 bus converter. Also used the EGA board. With those two boards I can "most of the time" get a stable display using the 8088. Very long story short, it's apparent that the timing specifications for these VGA chips is very tight. I still have not given up, but a solution will require a painstaking comparison of most ISA signals in a PC motherboard and the corresponding ones in the S100 bus. Long term the idea was to get this converter board working and then strip down the interface so the video chips are talking directly to the S100 bus. The recent "discovery" of GAL's has changed much of the above. I took one try, 8 bit CGA's look good but I have had to do yet another prototype which Andrew is now laying out. Could all the above be done differently. Absolutely! It's crying out for a CPLD approach, but that is way above my capabilities. I was even thinking if we could use some modern very fast 32 bit CPU to interface between the two buses. However I think even today they would not be able to keep up to say a 10MHz Phi on the S100 bus. I'm attaching the core circuits so you get a flavor of things. Comments welcome From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] Sent: Wednesday, June 18, 2014 3:46 PM To: 'Charlie Carothers' Cc: n8vem...@googlegroups.com; mon...@vitasoft.org Subject: [N8VEM-S100:4271] RE: VGA chipset on S-100 bus Hi John Monahan is leading the effort for an S-100 SVGA board. Hopefully he can contact you for any help on the project. Thanks and have a nice day! Andrew Lynch From: Charlie Carothers [mailto:csqu...@tx.rr.com] Sent: Saturday, June 14, 2014 12:46 PM To: Andrew Lynch Subject: VGA chipset on S-100 bus Hi Andrew, I know it has been a long while - I'm *really* behind reading the classic computer emails - but I noticed just yesterday that on 8/8/13 you said: 3. S-100 TestIO V2 - An experimental S-100 to ISA bridge. The purpose of this board is to diagnose why the VGA chipset works on the ISA bus but not on the S-100 bus. May evolve into a general purpose bridge board sometime in the future but is just for internal build and test at the moment. I was just wondering which VGA chipset you were using, and whether you got it working? Quite a few years ago we worked through the connection of a Chips and Technology 65545 video controller to an 80386EX at work. It was not a lot of fun! Our first interface was to 320x240 quarter VGA color and mono displays. Later, we also supported a full 640x480 color display. If you've ever used an ATM with the "Tidel" logo you've seen the result (except for the very early ones which used a plasma display). Our EE (Jim) said he was told that interfacing the 65545 to the memory and address bus of the 386 was impossible, but we did it anyway. He did use a CPLD to help with some of the interface. The only thing that never quite worked correctly was reading the video RAM from the 386. I did a little diagnostic that read it and wrote it back to the same locations. When we ran that, a nice colored checkerboard would slowly turn to mush. Fortunately that was not a system requirement, so it did not really matter. Jim and I talked about it some, and he always thought he could fix it with some CPLD changes but there was never any time available to do that since it was not critical. We were very small fish in C&T's water, so they were not a lot of help, like zero. I remember the final connection that made it work was a pin that had to be grounded which was only explained in the data sheet for a predecessor chip! I have no idea if you're still working on this, or if you're still having any problems with it. If you are, and there is anything I could help you with I'd be happy to try. I no longer have an operational board and display from that project, but I do have the schematics and the software source code we used. I might have a copy of the CPLD code, but I'm not sure about that. csqu...@tx.rr.com -- Later, Charlie C. @CSquared70 In God We Trust!!! (and He is in control!) -- You received this message because you are subscribed to the Google Groups "N8VEM-S100" group. To unsubscribe from this group and stop receiving emails from it, send an email to n8vem-s100+...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
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