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RE: [N8VEM-S100:4308] Re: lessons learned building an SMB board set

Frank the IEEE-696 specs state that the address lines are stable when pSYNC is high AND when pSTVAL* is low.   That is why  both are used on the V2 SMB.    For low speed CPU like the Big Z board I think you should be able to get away with just pSYNC. So try bending up pin 13 of U10.   If that works make a solder connection on the chip pins so both are driven by pSYNC only.


Some early S100 companies simply inverted PHI to generate pSTVAL.    This caused problems with other manufacturers boards. That is why for example I have the jumper JP10 for use with the SD Systems Versafloppy II board which sends the inverted PHI to a reserved S100 line.





From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Frank Schieschke
Sent: Friday, June 20, 2014 11:54 AM
To: n8vem...@googlegroups.com
Subject: [N8VEM-S100:4308] Re: lessons learned building an SMB board set


My SMB boards arrived yesterday.
Thank Todd, for that perfect service.
I have it up and it is running at once without problems.
My first object to monitoring is a Jade Big Z based computer.
The SMB shows the correct data, but the address allways stay at 000000.
I find that the address latch logic neede a valid pSTVAL signal.
The JADE board have instead PHI1 connected to pin 25, which i have cutted.
Any thougth for building a vald pSTVAL signal?


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