Thanks Leon! Here are the updated schematic and PCB layout files for the S-100 VDP. I’ll post these again so if anyone else has any fixes and/or changes we can get those in before ordering prototype boards. I think we are pretty much ready to go through. I am going to start investigating on what the remainder of IO and memory would be necessary for another separate board. I’d like to make it to be generally useful for builders and also provide as much hardware compatibility as possible. I am still thinking this through. Basically it looks like a 64K SRAM, a 8255 PIO for internal configuration, and a cartridge port. I appreciate all your dedication and hard work on the S-100 VDP project. I am sure you’ve saved this board project. Thanks and have a nice day! From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Leon Byles Hi John, The signals on K17 pin1 and pin2 should be swapped. U25 pin7 is the input. It looks good apart from that. Best regards Leon From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Andrew Lynch D’oh! I was wondering about that. Is this what you meant? Murphy’s Law is alive and well. What can be misinterpreted will be! Please review and send me any changes and/or corrections. Thanks and have a nice day! From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Leon Byles Sorry Andrew, when I said p7, I meant pin 7 not the color bus signal P7. Leon Andrew I have checked the S100_VDP V3-sch schematic and found a few mods I have on my board that are missing: 1. On the RAMDAC U25 p7 can we put a two way jumper in to take the BLANK signal either from the VDP U12 p7 (as it is wired now) or to have it pulled up to 5V via a 1k pull-up so it is permanently unblanked? The only way I could get any output from the RAMDAC was to cut the BLANK signal from the VDP (U12) by slipping out pin 7 from the socket and pulling up U25 p7. 2. I have a 1k pull-up on the VDP U12 p2 DHCLK. This is an open drain output so it needs to be pulled up. I am not actually running the RAMDAC from the DHCLK at the moment but we would need the pull-up to get full TTL levels if we wanted to use it. Best regards Leon Byles From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Andrew Lynch Hi! Please review the attached S-100 VDP V3 schematic and PCB layout files and send me any changes and/or corrections. These include the latest changes from Leon and John. Any others? Assuming we are good to go on this board, I will send it for prototype PCBs soon. Thanks and have a nice day! -- -- -- -- |
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Printing S100_VDP V3-sch.pdf
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