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S-100 80386 CPU Board V03 - Master/Slave Switch Timing Problem ??

Hi John,

I seen to have run into an issue with the recently released 80386 board involving the above subject.

My hardware is:-
S-100 Computers Propeller Console
S-100 Computers 16MB SRAM V3
S-100 Computers MS-DOS Board V2
S-100 Computers Z80 Master CPU Board
S-100 Computers 80386 CPU Board V03 (configured as slave)
S-100 Computers ZFDC
S-100 Computers CF/IDE Board V2
10 slot active terminated backplane

The situation is, I can bring up the above system to Z80 monitor and press 'O' or 'W' to transfer control to the 80386 monitor, Then from within the 80386 monitor I can press 'Z' to transfer control back to the Z80 monitor, I could do this all day long and it works reliably.

The issue is that when I am in the 80386 monitor (real mode) if I press the 'N' key to enter  the IDE menu the 80386 CPU card drops out of control and hands back control to the Z80 monitor. I have spend a few hours looking into this and found that when the 'N' menu item is pressed the 'D' type flip flop U91A is falsely triggered providing the initiation of transfer back to the Z80 monitor. If when the 80386 card is active I remove jumper P67 1-2 allowing U52C to float high then I can enter menu item 'N' and access the IDE menu fine, obviously I can not then transfer back to the Z80 without replacing the link.

I compared this part of the circuit with that of the 80286 board which works perfectly in my system running either it's on board 80286 Eproms or the 80386 Eprom code on the MS-DOS board.
Both boards in essence use the same circuit to handle the port EDH switchover function but I did notice that on the 286 the address lines are buffered, on the 386 they are not.
To cut a long story short I have substituted, a 74F00 into position U52 and replaced U55 with a 74LS244 as suggested in your listing, this has helped the situation and I can now get to the IDE menu 50% of the time, so it would seem to me that some spurious/possible timing condition is occurring causing the false trigger. Changing the 80386 CPU clock frequency doesn't help, I have tried 40Mhz, 30 Mhz & 16MHz clocks, all IC's on the board are new Texas Instruments parts.

I have not yet build the SMB board yet so I rely on the on board port EDH circuit for bus handover.

I also do not yet own a logic analyser,, would it be possible for you confirm if the timing is 'that' tight around this part of the circuit, and can you reproduce the problem in a system without a SMB board ??

many thanks in anticipation

David Fry

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