Hi Dave, Here is an idea that may help with your 6809 and 6502 interests. What about an "Ultimate 8 bit CPU board"? Instead of having a board like the ECB 6X0X, where you choose between a 6502 or a 6802 or a 6809 at construction time, why not have a board with a 6502 AND a 6802 AND a 6809 and choose between them at run time? The Euro card based wire wrapped machine I constructed in 1983 has a 68B09E, a 68B00, a Z80A and an RCA 1802E (see attached pictures). At power on or after a master reset the 6809 is enabled. Switching between CPUs is achieved by using the halt (or bus) request system of each CPU. [Note the 1802 doesn't have a halt request/halt acknowledge system. I had to build my own using the wait control. Something similar will need to be designed for the 6502 since it also doesn't have a bus request system.] There are 3 sets of registers that control CPU selection (look at the lower left corner of the attached Bboard.jpg). To change CPU, the new CPU's number is written to address F020 (0=6809 1=6800 2=Z80 3=1802). If you wish to return to the original CPU you write 1 (6809), 2 (6800), 4 (Z80) or 8 (1802) to F021 (WARMREG). Doing this will allow the previously selected CPU to continue from where it stopped if control is returned to it. If a CPU's "WARMREG" bit is zero, that CPU will be reset following a CPU transfer. Writing to address F022 triggers the transfer process. The current CPU receives a halt request, the resulting halt acknowledge (note that the "HA" inputs to the LS153 "Y" are active low not as shown) transfers the CPU number from LS74 "I" to LS74 "M" which either releases RESET or HALT on the new CPU. Things I would change from my design. 1) I wanted to use Motorola peripherals, the I/O board has 2 68B50s, 2 68B21s and a 6522A, so this required the generation of a fake "E" clock for the Z80 and 1802. It would probably be better to use '80 type peripherals and generate rd are wr signals for them. 2) More thought is required for the interrupt system. The "piggy back" LS541 on the CPUs board is providing a vector address for the Z80 (which is in Interrupt Mode 2). 3) The I/O instructions on the Z80 and 1802 are not used, all the I/O is memory mapped. This could be bad or good depending on your point of view. As to selecting which processors to use - I can only think of 5 possible candidates that are readily available Z80/6802/6809/6502/1802 or 1806 (and they all also have disk operating systems available). I can't see any point in using an 8085 if you have a Z80 and things like the SC/MP and 2650 are not readily available (and have paged memory maps). I chose to use a 68B09E and a 68B00 only because I had the chips. I don't think there is any reason why you couldn't substitute with a 68B09 and 68B02. The disadvantage of having more than 4 processors is that the LS139s and LS153s will have to be replaced with LS138s and LS151s which will therefore require more ICs. So having a maximum of 4 CPUs may be necessary. I would therefore suggest a 4 CPU board with a Z80, 6809, 6802 and 6502. (The reason for the 1802 was that my first machine was a COSMAC VIP. Mine is wildly over-clocked to 8 MHz [not the 4MHz shown on the circuit], most 1802 designs were clocked at less than 2 MHz so mine is a relative speed demon.) There is also the question of whether to build an ECB bus or S-100 card. The S-100 philosophy of one card - one function, as well as more board space, makes it the most likely candidate. The bus of my system is very simple and is not much more than the address and data buses, the r/w and E clock yet it still required 2 cards for just the CPU. Even if 220 mm depth ECB bus boards were used there probably won't be enough space for RAM and I/O chips. A 3 board ECB bus solution may be necessary. I was planning to develop something along these lines with one of the regular S-100 prototype cards, but realistically it will take me a long time to get to it, so I'm tossing this idea out there for other people to think about. I'm also happy to answer any questions anyone has about the design. Cheers, Ian.
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