Steven, I sent a status update on our V2-SMB a few days. In case you dig not see it. Her it is again:- Andrew and I have been working on a V2 System Monitor Board for some time. Already have done one prototype but another is needed and is in the works. FYI I am attaching a schematic. The issue is mainly how much can you get on one board. The current V2 has the following:- Display 24 address lines with either a HEX display or Bar LED’s (cheaper) Display 8 or 16 bit data lines coming into the current bus master in halt/single step mode Set a hardware (24 switches) breakpoint anywhere in the current masters 24 bit address space so once the CPU accesses that location it halts and can be single stepped from there. A Single step function. Lower any combination of the 4 TMA(DMA) S100 lines so that in theory, up to 16 CPU’s could control the bus. 555 Timer generated (long) signals for reset and slave clear. All address lines are now latched so fast CPU’s like an 80386 can display valid data on the HEX display. LED (stretched) light flashes and status signals for the major S100 bus status/control signals, (pWR*, SOUT, MWRT etc.). These remain valid during single step mode. A few other tweaks. The only major IMSAI function not included is “deposit” and “deposit next”. These were too difficult to add in a generalized manner independent of CPU speed (i.e. no single shots) and can easily and better done via the current master/CPU monitor. We are just doing a second prototype version and hope to have it in a few weeks. I don’t anticipate any further issues but did not want to go for a final “production” run because there were numerous small changes on the previous prototype. Should have it running in say a month. Stay tuned and keep an eye on this forum. BTW, the main issue with older front panel boards and the FPMini board, jade board etc. is that they use LS123 single shots etc. to emulate signals. These simply will not work correctly with high bus speeds. There are of course ways around that but it uses up board real estate. For the SMB, I make sure all signals are clock speed independent (e.g. latching address lines etc.). John John From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of Steven Feinsmith I purchased four superb designed S-100 buffered boards few weeks ago and I was very please with it. I also interest to buy S-100 non-buffered prototype boards for my project that involve to clone from my aged Technical Design Labs boards (ZPU, SMB and Z16). I am sure that you may also need it for your future projects with wirewarp method. -- |
Attachment:
Printing S100_SMB V2-Rerun 3-sch.pdf
Description: Adobe PDF document