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RE: [N8VEM-S100:6291] Re: An updated (V3) version of our Dual IDE/CF card S100 bus board

Thanks Ian and Dave for those points/suggestions.

One confusing thing is in what respect are we talking about read and write. In terms of the S100 bus/CPU or the 8255.    Let’s talk in terms of the CPU.

Dave since you feel the problem is just with the CPU WR* signal  (particularly the 68K), then I will go back to using the 74LS244 for the CPU read (S100 bus DI lines).


Within the GAL:-

/SELECT_BOARD  =  (port address lines) * sOUT

                                      + (port address lines) * sINP


/RD                           =   /SELECT_BOARD  *  /pDBIN

/WR                         =  /SELECT_BOARD   *  /pWR


The U110 would be OE* (Low) when SELECT_BOARD* & RD* are low (U107a).

On the 8255 its CS* will go low with SELECT_BOARD*, its RD pin (5) would go low with /RD from the GAL.   It would present data on the boards bidirectional bus for U110.  The would be some lag here because the 8255 can only get stared when /RD is low but since the S100 bus CPU has until the pDBIN signal goes low again we should be OK.

On the CPU write side of things, early on we setup the U108 OE* for output.  U107b is gated only by SELECT_BOARD* and the inverted S100 bus line sOUT.  Data is clocked into the U108 by a slightly delayed WR.  The LS373 accepts data when its LE is HIGH, latching and holding it when it returns low.  On the 8255 side, the RD signal (pin36) sees the same WR* signal but because the data is now latched in the LS373 has extra time to input the data.  See attached schematic.


Guys could you carefully look at mu y logic here.  This could be a critical issue and done properly could give us a much better board at high speeds.






From: n8vem...@googlegroups.com [mailto:n8vem...@googlegroups.com] On Behalf Of yoda
Sent: Wednesday, February 11, 2015 8:37 AM
To: n8vem...@googlegroups.com
Subject: Re: [N8VEM-S100:6291] Re: An updated (V3) version of our Dual IDE/CF card S100 bus board


I would just solve the problem which is write and not deal with read - reads seem to be OK.  I would invert the RD* and use it as OE* and get rid of the read latch.  So the data will stay there until a read is done and then the latch will be tristated.  Keep it simple.  I may not be describing it correctly but just leave the data latched and enabled except for when you are doing reads.  I think that will solve the problem.

On Wednesday, February 11, 2015 at 3:09:34 AM UTC-6, Ian May wrote:

Hi John,

You can't use '374 latches because the 8255 won't have any data setup time before the WR line goes high (100ns min in the datasheet I looked at) and by gating the '374 OE with the WR line you still may not have enough data hold time. Perhaps a '373 and two series inverters on the WR line would work, the first inverter driving the '373 LE and the second driving the '373 OE. The 8255 would then have WR going high two inverter delays before the '373 outputs start going tristate. There is again a potential data hold time problem this time with a 74LS373 which has a minimum hold time of 20ns. Add an LS inverter delay and you are near the 30ns the 8255 needs. The data setup time for a 74F373 is 3ns minimum so it may be a better choice.




On Wed, Feb 11, 2015 at 6:09 PM, monahanz <mon...@vitasoft.org> wrote:

There was an error in the schematic I had the sINP & sOUT inputs to U107A flipped the wrong way. Attached is the correct schematic

On Tuesday, February 10, 2015 at 11:17:58 PM UTC-8, monahanz wrote:

Dave that's a very good point. There is no harm in latching the data, at worse it would have no effect, and possibly be very benificial.

I have come up with the idea of using two 74LS374's instead of the 74LS244 for the onboard bidirectional data bus to the 8255.  The LS374's latch their inputs on clock low to high so we can use the RD* and WR* signals comming from the GAL.  Fortunately the 8255 also uses WR* and RD* (lows).


The SELECT_BOARD* will now go low for EITHER a port read or write. The S1oo bus sOUT & sINP status lines will keep the U108 & U110 gates open as long as possible and the RD* and WR* will latch the data.   Probably not necessary to have data FROM the 8255 latched but may as well do both.


Could you take a glance at the circuit include here.


On Tuesday, February 10, 2015 at 9:23:42 PM UTC-8, yoda wrote:

Hi John

My comment is I am not sure that the 8255 is not the root of the problems at higher frequencies.  Having to have the data valid for a min of 30 nsec after pWR* is de-asserted is going to be a problem.  The GAL will help some but I think you would be served better by latching the data on the board.  This is the only board so far that I have not been able to get to work with the 68k board.  I will certainly take a couple of boards and see if it works better but if you are going to do a tweak on the board at least latch the data on write to 8255 if you insist on keeping it 8255 based.


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